RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 186 of 920
Dec 22, 2016
(2) Default level of TOmn pin and output level after timer operation start
The change in the output level of the TOmn pin when timer output register m (TOm) is written while timer
output is disabled (TOEmn = 0), the initial level is changed, and then timer output is enabled (TOEmn = 1)
before port output is enabled, is shown below.
(a) When operation starts with master channel output mode (TOMmn = 0) setting
The setting of timer output level register m (TOLm) is invalid when master channel output mode
(TOMmn = 0). When the timer operation starts after setting the default level, the toggle signal is
generated and the output level of the TOmn pin is reversed.
Figure 7 - 35 TOmn Pin Output Status at Toggle Output (TOMmn = 0)
Remark 1. Toggle: Reverse TOmn pin output status
Remark 2. m: Unit number (m = 0), n: Channel number (n = 3)
Initial
status
Hi -Z
Port output is enabled
Toggle Toggle Toggle Toggle Toggle
TOmn
(Output)
TOEmn
TOmn bit = 0
(Initial status: low)
TOmn bit = 1
(Initial status: high)
TOmn bit = 0
(Initial status: low)
TOmn bit = 1
(Initial status: high)
TOLmn bit = 0
(Active high)
TOLmn bit = 1
(Active low)
Bold line: active level
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