RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 204 of 920
Dec 22, 2016
Figure 7 - 52 Example of Basic Timing of Operation as Input Pulse Interval Measurement (MDmn0 = 0)
Remark 1. m: Unit number (m = 0), n: Channel number (n = 3)
Remark 2. TSmn: Bit n of timer channel start register m (TSm)
TEmn: Bit n of timer channel enable status register m (TEm)
TImn: TImn pin input signal
TCRmn: Timer count register mn (TCRmn)
TDRmn: Timer data register mn (TDRmn)
OVF: Bit 0 of timer status register mn (TSRmn)
TSmn
TEmn
TImn
TDRmn
TCRmn
0000H
c
b
0000H
a
c
d
INTTMmn
ba
d
OVF
FFFFH