RL78/G1H CHAPTER 13 A/D CONVERTER
R01UH0575EJ0120 Rev. 1.20 Page 304 of 920
Dec 22, 2016
Figure 13 - 16 Conversion Operation of A/D Converter (Software Trigger Mode)
In one-shot conversion mode, the ADCS bit is automatically cleared to 0 after completion of A/D conversion.
In sequential conversion mode, A/D conversion operations proceed continuously until the software clears bit 7
(ADCS) of the A/D converter mode register 0 (ADM0) to 0.
Writing to the analog input channel specification register (ADS) during A/D conversion interrupts the current
conversion after which A/D conversion of the analog input specified by the ADS register proceeds. Data from the
A/D conversion that was in progress are discarded.
Reset signal generation clears the A/D conversion result register (ADCR, ADCRH) to 0000H or 00H.
Conversion time
Sampling
time
A/D conversion
Undefined
SAR
ADCR
INTAD
1 is written to ADCS
Conversion start
A/D converter
operation
Sampling
Conversion
result
Conversion
result
ADCS
Conversion
start time
Conversion
standby
Conversion
standby
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