Note 1. If the A/D conversion end interrupt request signal (INTAD) is not generated by setting ADRCK bit and ADUL/ADLL
The system enters the STOP mode again. If a hardware trigger is input later, A/D conversion operation is again
performed in the SNOOZE mode.
Note 2. If the AWC bit is left set to 1, A/D conversion will not start normally in spite of the subsequent SNOOZE or normal
operation mode. Be sure to clear the AWC bit to 0.
Start of setup
PER0 register setting
• ADM0 register
FR2 to FR0, LV1, LV0 bits: These are used to specify the A/D conversion time.
• ADM1 register
ADTMD1, ADTMD0 bits: These are used to specify the hardware trigger wait mode.
ADSCM bit: One-shot conversion mode
ADTRS1, ADTRS0 bits: These are used to select the hardware trigger signal .
• ADM2 register
ADREFP0 ADREFM bits: These are used to select the reference voltage .
ADCRK bit: This is used to select the range for the A/D conversion result comparison
value generated by the interrupt signal from AREA 1, AREA3, and AREA2.
ADTYP bit: 8-bit/10-bit resolution
• ADUL/ADLL register
These are used to specify the upper limit and lower limit A /D conversion result
comparison values.
• ADS register
ADS4 to ADS0 bits: These are used to select the analog input channels .
• ADM0 register setting
• ADM1 register setting
• ADM2 register setting
• ADUL/ADLL register setting
• ADS register setting
(The order of the settings is
irrelevant.)
AWC = 1
Enter the STOP mode
ADCE bit setting
End of A/D conversion
Hardware trigger generation
Immediately before entering the STOP mode, enable the SNOOZE mode by setting the
AWC bit of the ADM2 register to 1.
After hardware trigger is generated, the system automatically counts up to the
stabilization wait time for A/D power supply and A/D conversion is started in the
SNOOZE mode.
The conversion results are stored in the ADCR and ADCRH registers.
The AWC bit of the ADM2 register is set (1), and the system enters the A/D conversion
standby status.
The A/D conversion end interrupt (INTAD) is generated.
Note 1
Storage of conversion results
in the ADCR and ADCRH
registers
AWC = 0
Normal operation
Release the SNOOZE mode by clearing the AWC bit of the ADM 2 register to 0.
Note 2
The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.
ADPC and PMCx
register settings
The ports are set to analog input.
ANI0 to ANI2, ANI13, and ANI14 pins: Set using the ADPC register
ANI19 pin: Set using the PMCx register
PMx register setting
The ports are set to the input mode.
The A/D conversion operations are performed.
INTAD
generation?
Yes
No
The clock request signal
(an internal signal) is
automatically set to the low
level in the SNOOZE mode.
Normal
operation
SNOOZE
mode
STOP
mode
Normal
operation
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