RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 365 of 920
Dec 22, 2016
(1) Register setting
Figure 14 - 32 Example of Contents of Registers for Master Reception of 3-Wire Serial I/O (CSIp)
(a) Serial mode register mn (SMRmn)
(b) Serial communication operation setting register mn (SCRmn)
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
(d) Serial output register m (SOm)... Sets only the bits of the target channel.
(e) Serial output enable register m (SOEm)... The register that not used in this mode.
(f) Serial channel start register m (SSm)... Sets only the bits of the target channel to 1.
Remark : Setting is fixed in the CSI master reception mode,
: Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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SMRmn
CKSmn
0/1
CCSmn
0
0 0 0 0 0
STSmn
0 0
SISmn0
0 1 0 0 0
MDmn1
0
MDmn0
0/1
Operation clock (fMCK) of channel n
0: Prescaler output clock CKm0 set by the SPSm register
1: Prescaler output clock CKm1 set by the SPSm register
Interrupt source of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
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SCRmn
TXEmn
0
RXEmn
1
DAPmn
0/1
CKPmn
0/1
0
EOCmn
0
PTCmn1
0
PTCmn0
0
DIRmn
0/1 0
SLCmn1
0
SLCmn0
0 0 1 1
DLSmn0
0/1
Selection of data transfer sequence
0: Inputs/outputs data with MSB first
1: Inputs/outputs data with LSB first
Setting of data length
0: 7-bit data length
1: 8-bit data length
Selection of the data and clock phase (For
details about the setting, see
14.3
Registers Controlling Serial Array Unit
.)
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SDRmn
Baud rate setting
(Operation clock (f
MCK) division setting) 0
Receive data
(Write FFH as dummy data.)
SIOp
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SOm
0 0 0 0
CKOm3
0/1
CKOm2
0/1
CKOm1
0/1
CKOm0
0/1 0 0 0 0
SOm3
×
SOm2
×
SOm1
×
SOm0
×
Communication starts when these bits are 1 if the clock phase is
non-reversed (the CKPmn bit of the SCRmn = 0). If the clock phase is
reversed (CKPmn = 1), communication starts when these bits are 0.
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SOEm
0 0 0 0 0 0 0 0 0 0 0 0
SOEm3
×
SOEm2
×
SOEm1
×
SOEm0
×
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SSm
0 0 0 0 0 0 0 0 0 0 0 0
SSm3
0/1
SSm2
0/1
SSm1
0/1
SSm0
0/1
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