Renesas RL78/G1H User Manual

RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 371 of 920
Dec 22, 2016
Figure 14 - 39 Flowchart of Master Reception (in Continuous Reception Mode)
Note For the initial setting, refer to Figure 14 - 33.(Select buffer empty interrupt)
Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 14 - 38 Timing Chart of Master Reception (in Continuous
Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0).
Starting CSI communication
Wait for receive completes
Clear interrupt request flag (XXIF), reset interrupt mask
(XXMK) and set interrupt enable (EI)
Reading receive data to SIOp
(= SDRmn [7:0])
Setting receive data
Setting storage area of the receive data, number of
communication data
(Storage area, Reception data pointer, Number of
communication data and Communication end flag are
optionally set on the internal RAM by the software)
Enables interrupt
Writing dummy data to
SIOp (= SDRmn [7:0])
Writing to SIOp makes SCKp
signals out (communication starts)
BFFmn = 1?
Buffer empty/transfer end interrupt
When interrupt is generated, it moves to
interrupt processing routine
No
Read receive data, if any, then write them to
storage area, and update receive data pointer
(also subtract -1 from number of transmit data)
When number of communication data
becomes 0, receive completes
Yes
<1>
<2>
<3><6>
End of communication
Disable interrupt (MASK)
Subtract -1 from number of
transmit data
Number of communication
data?
Clear MDmn0 bit to 0
Writing dummy data to
SIOp (= SDRmn [7:0])
RETI
Number of communication
data = 0 ?
Yes
Write MDmn0 bit to 1
Communication continued?
<4>
<7>
<5>
<2>
No
SAU default setting
= 0
= 1
No
Yes
≥ 2
Write STmn bit to 1<8>
Main routineInterrupt processing routineMain routine
Note

Renesas RL78/G1H Specifications

General

Brand	Renesas
Model	RL78/G1H
Category	Microcontrollers
Language	English