Starting setting
Wait for transmission
completes
Clear interrupt request flag (XXIF), reset interrupt mask
(XXMK) and set interrupt enable (EI)
Read receive data to SIOp
(= SDRmn [7:0])
Setting
transmission/reception data
Setting storage area and number of data for transmission/reception
data
(Storage area, Transmission/reception data pointer, Number of
communication data and Communication end flag are optionally set
on the internal RAM by the software)
Enables interrupt
BFFmn = 1?
Buffer empty/transfer end interrupt
When buffer empty/transfer end is
generated, it moves interrupt
processing routine
No
Other than the first interrupt, read reception data
then writes to storage area, update receive data
pointer
Yes
<1>
<3><6>
End of communication
Disable interrupt (MASK)
Subtract -1 from number of
transmit data
Number of communication
data?
RETI
Number of communication
data = 0?
Yes
Write MDmn0 bit to 1
Communication
continued?
<4>
<7>
<5>
No
SAU default setting
= 0
≥ 2
No
Yes
= 1
Writing transmit data to
SIOp (= SDRmn [7:0])
Clear MDmn0 bit to 0
Start communication when master start
providing the clock
If transmit data is remained, read it from storage area
and write it to SIOp. Update storage pointer.
If transmit completion (number of communication data
= 1), Change the transmission completion interrupt
Yes
Write STmn bit to 1<8>
Main routineInterrupt processing routineMain routine
Note