Renesas RL78/G1H User Manual

RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA
R01UH0575EJ0120 Rev. 1.20 Page 428 of 920
Dec 22, 2016
Figure 15 - 1 Block Diagram of Serial Interface IICA (channel 0)
Slave address
register 0 (SVA0)
ACK
generator
Data hold
time correction
circuit
IICA shift
register 0 (IICA0)
Stop condition
detector
Noise
eliminator
Serial clock
counter
Interrupt request
signal generator
Serial clock
controller
Counter
Serial clock
wait controller
Wakeup
controller
Noise
eliminator
ACK detector
Internal bus
IICA status register 0 (IICS0)
Filter
Filter
Controller for
STOP mode
Bus status
detector
Match
signal
Match signal
DQ
Set
Clear
IICWL0
TRC0
DFC0
DFC0
SDAA0/
P61
Start
condition
generator
Stop
condition
generator
Output control
IICA low-level width
setting register 0 (IICWL0)
INTIICA0
IICCTL00.STT0, SPT0
IICS0.MSTS0, EXC0, COI0
IICS0.MSTS0, EXC0, COI0
IICCTL01.PRS0
f
CLK
Start condition
detector
Internal bus
PM61
Output
latch (P61)
PM60
Output
latch (P60)
IICA high-level width
setting register 0 (IICWH0)
WUP0
N-ch open-
drain output
SCLA0/
P60
N-ch open-
drain output
f
CLK/2
IICA control register 01
(IICCTL01)
IICA flag register 0
(IICF0)
WUP0 CLD0 DAD0 SMC0 DFC0 PRS0
STCF0 IICBSY0 STCEN0 IICRSV0
SO latch
MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0
IICA control register 00
(IICCTL00)
IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0
IICA shift register 0 (IICA0)
Selector
fMCK

Renesas RL78/G1H Specifications

General

Brand	Renesas
Model	RL78/G1H
Category	Microcontrollers
Language	English