RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA
R01UH0575EJ0120 Rev. 1.20 Page 444 of 920
Dec 22, 2016
Figure 15 - 15 Format of IICA control register n1 (IICCTLn1) (2/2)
Caution 1. The maximum operating frequency of the IICA operating clock (fMCK) is 20 MHz (Max.). Only when
f
CLK exceeds 20 MHz, set bit 0 (PRSn) of IICA control register n1 (IICCTLn1) to 1.
Caution 2. Note the minimum f
CLK operating frequency when setting the transfer clock. The minimum fCLK
operating frequency for serial interface IICA is determined according to the mode.
Fast mode: f
CLK = 3.5 MHz (MIN.)
Fast mode plus: f
CLK = 10 MHz (MIN.)
Normal mode: f
CLK = 1 MHz (MIN.)
Caution 3. The fast mode plus is only available in the products for “A: Consumer applications (T
A = -40 °C to +85
°C)” and “D: Industrial applications (TA = -40 °C to +85 °C)”.
Remark 1.
IICEn: Bit 7 of IICA control register n0 (IICCTLn0)
Remark 2. n = 0, 1
CLDn Detection of SCLAn pin level (valid only when IICEn = 1)
0 The SCLAn pin was detected at low level.
1 The SCLAn pin was detected at high level.
Condition for clearing (CLDn = 0) Condition for setting (CLDn = 1)
• When the SCLAn pin is at low level
• When IICEn = 0 (operation stop)
• Reset
• When the SCLAn pin is at high level
DADn Detection of SDAAn pin level (valid only when IICEn = 1)
0 The SDAAn pin was detected at low level.
1 The SDAAn pin was detected at high level.
Condition for clearing (DADn = 0) Condition for setting (DADn = 1)
• When the SDAAn pin is at low level
• When IICEn = 0 (operation stop)
• Reset
• When the SDAAn pin is at high level
SMCn Operation mode switching
0 Operates in standard mode (fastest transfer rate: 100 kbps).
1 Operates in fast mode (fastest transfer rate: 400 kbps) or fast mode plus (fastest transfer rate: 1 Mbps).
DFCn Digital filter operation control
0 Digital filter off.
1 Digital filter on.
Use the digital filter only in fast mode and fast mode plus.
The digital filter is used for noise elimination.
The transfer clock does not vary, regardless of the DFCn bit being set (1) or cleared (0).
PRSn Operation clock (f
MCK) control
0 Selects f
CLK (1 MHz ≤ fCLK ≤ 20 MHz)
1 Selects f
CLK/2 (20 MHz ≤ fCLK)
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