RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA
R01UH0575EJ0120 Rev. 1.20 Page 502 of 920
Dec 22, 2016
Figure 15 - 41 Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/4)
(2) Address ~ data ~ data
Note 1. Write data to IICAn, not setting the WRELn bit, in order to cancel a wait state during transmission by a master device.
Note 2. For releasing wait state during reception of a slave device, write “FFH” to IICAn or set the WRELn bit.
Remark n = 0, 1
ACKDn
(ACK detection)
IICAn
WTIMn
(8 or 9 clock wait)
ACKEn
(ACK control)
MSTSn
(communication status)
STTn
(ST trigger)
SPTn
(SP trigger)
WRELn
(wait cancellation)
INTIICAn
(interrupt)
Bus line
TRCn
(transmit/receive)
Master side
SCLAn (bus)
(clock line)
SDAAn (bus)
(data line)
Slave side
IICAn
ACKDn
(ACK detection)
STDn
(ST detection)
SPDn
(SP detection)
WTIMn
(8 or 9 clock wait)
ACKEn
(ACK control)
MSTSn
(communication status)
WRELn
(wait cancellation)
INTIICAn
(interrupt)
TRCn
(transmit/receive)
D16D15D14D13D12D11 D27
: Wait state by slave device
: Wait state by master and slave devices
Note 2
ACK
<5>
<7>
<8>
<9>
<10>
D17
Note 1
D10
ACKW
Note 2<6>
<4>
<3>
Note 1
H
H
L
L
H
H
L
L
H
L
H
L
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