RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA
R01UH0575EJ0120 Rev. 1.20 Page 510 of 920
Dec 22, 2016
Figure 15 - 45 Example of Slave to Master Communication
(When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/3)
(2) Address ~ data ~ data
Note 1. For releasing wait state during reception of a master device, write “FFH” to IICAn or set the WRELn bit.
Note 2. Write data to IICAn, not setting the WRELn bit, in order to cancel a wait state during transmission by a slave device.
Remark n = 0, 1
ACKDn
(ACK detection)
IICAn
WTIMn
(8 or 9 clock wait)
ACKEn
(ACK control)
MSTSn
(communication status)
STTn
(ST trigger)
SPTn
(SP trigger)
WRELn
(wait cancellation)
INTIICAn
(interrupt)
Bus line
TRCn
(transmit/receive)
Master side
SCLAn (bus)
(clock line)
SDAAn (bus)
(data line)
Slave side
IICAn
ACKDn
(ACK detection)
STDn
(ST detection)
SPDn
(SP detection)
WTIMn
(8 or 9 clock wait)
ACKEn
(ACK control)
MSTSn
(communication status)
WRELn
(wait cancellation)
INTIICAn
(interrupt)
TRCn
(transmit/receive)
<5>
<8>
D10 D27
ACK
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices
D16D15D14D13D12D11
<11>
<4>
<9>
Note 1
R D17
ACK
Note 1
<7>
<3> <10>
Note 2 Note 2
<12>
<6>
L
H
L
H
H
L
L
H
L
L
H
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