RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC)
R01UH0575EJ0120 Rev. 1.20 Page 515 of 920
Dec 22, 2016
Note In the SNOOZE mode, these areas cannot be set as the sources for DTC transfer since the flash memory is stopped.
Remark i = 0 to 4, j = 0 to 23
Interrupt request Normal mode When the data transfer causing the DTCCTj register value to change from 1 to 0 is performed, the
activation source interrupt request is generated for the CPU, and interrupt handling is performed on
completion of the data transfer.
Repeat mode When the data transfer causing the DTCCTj register value to change from 1 to 0 is performed while the
RPTINT bit in the DTCCRj register is 1 (interrupt generation enabled), the activation source interrupt
request is generated for the CPU, and interrupt handling is performed on completion of the transfer.
Transfer start When bits DTCENi0 to DTCENi7 in the DTCENi registers are 1 (activation enabled), data transfer is
started each time the corresponding DTC activation sources are generated.
Transfer stop Normal mode • When bits DTCENi0 to DTCENi7 are set to 0 (activation disabled).
• When the data transfer causing the DTCCTj register value to change from 1 to 0 is completed.
Repeat mode • When bits DTCENi0 to DTCENi7 are set to 0 (activation disabled).
• When the data transfer causing the DTCCTj register value to change from 1 to 0 is completed while
the RPTINT bit is 1 (interrupt generation enabled).
Table 16 - 1 DTC Specifications
Item Specification
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