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Renesas RL78/G1H - Page 608

Renesas RL78/G1H
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RL78/G1H CHAPTER 18 RF TRANSCEIVER
R01UH0575EJ0120 Rev. 1.20 Page 590 of 920
Dec 22, 2016
(24) Timer control register (BBTIMECON)
This register is used to control the timer in this transceiver.
The timer count enable bit controls the 32-bit timer count operation. Setting “1” enables the timer count. In
addition, setting “0” stops the timer while the count value is initialized to 00000000H.
The RF transmit can be started when the compare 0 value and timer value match by using the COMP0
transmit trigger enable bit. Warm-up starts immediately after the match and starts transmit after 350 μs. Be
sure to set these bit under the state they are IDLE.
The stamp timing switch bit can be used to select the stamp timing of the timer value. The value is updated
at the timing of receive start regardless of the address filter function when selecting the receive start time.
The COMP0 trigger function select bit can be used to select the CSMA-CA for the start function when
COMP0TRG is enabled.
The stamp value read switch bit can be used to select the time stamp register read value among the receive
start stamp value, receive completion stamp value, and the transmission completion stamp value.
The count source switch bit can be used to select the count source for the timer count between the
prescaler output and the data rate.
The BBTIMECON register is set by the serial interface in 8-bit units.
Reset signal generation clears this register to 00H.

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