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Renesas RL78/G1H - Page 617

Renesas RL78/G1H
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RL78/G1H CHAPTER 18 RF TRANSCEIVER
R01UH0575EJ0120 Rev. 1.20 Page 599 of 920
Dec 22, 2016
(31) Baseband interrupt enable register 2 (BBINTEN2)
This register is used to enable the baseband interrupt.
This register enables the interrupt output from the INTOUT pin upon generation of each interrupt. Set “1” to
the corresponding interrupt enable bit when you want to enable the interrupt output.
The BBINTEN2 register is set by the serial interface in 8-bit units.
Reset signal generation clears this register to 00H.
Figure 18 - 40 Baseband Interrupt Enable Register 2 (BBINTEN2) Format
Caution Be sure to clear bits 0 to 3 , 7 to “0”. These are read as X (undefined).
Address:
003BH
After reset: 00H R/W
Symbol76543210
BBINTEN2
X
BYTERCVINTEN
FLINTEN
RCVCUNTINTEN
X
X
XX
BYTERCVINTEN
Byte receive completion interrupt enable bit
0 Disabled
1 Enabled
FLINTEN Frame length interrupt enable bit
0 Disabled
1 Enabled
RCVCUNTINTEN
Number of received byte interrupt enable bit
0 Disabled
1 Enabled
<R>
<R>

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