Renesas RL78/G1H - Page 616

RL78/G1H CHAPTER 18 RF TRANSCEIVER
R01UH0575EJ0120 Rev. 1.20 Page 598 of 920
Dec 22, 2016
(30) Baseband interrupt enable register 1 (BBINTEN1)
This register is used to enable the baseband interrupt.
This register enables the interrupt output from the INTOUT pin upon generation of each interrupt. Set “1” to
the corresponding interrupt enable bit when you want to enable the interrupt output.
Set receive level filter interrupt enable bit (LVLFILINTEN) and receive level filter enable bit (LVLFILEN) to
"1" in initialization.
The BBINTEN1 register consists of 8 bits and can be accessed (serial interface communication) in 8 bit unit.
Reset signal generation clears this register to 00H.
Figure 18 - 39 Baseband Interrupt Enable Register 1 (BBINTEN1) Format
Address:
003AH
After reset: 00H R/W
Symbol76543210
BBINTEN1 LVLFILINTEN MODESWINTEN ROVRINTEN ADRSINTEN RCVSTINTEN RCV1INTEN RCV0INTEN RCVFININTEN
LVLFILINTEN Receive level filter interrupt enable bit
0 Disabled
1 Enabled
MODESWINTEN Mode switch receive completion interrupt enable bit
0 Disabled
1 Enabled
ROVRINTEN Receive Overrun interrupt enable bit
0 Disabled
1 Enabled
ADRSINTEN Address filter interrupt enable bit
0 Disabled
1 Enabled
RCVSTINTEN Receive start interrupt enable bit
0 Disabled
1 Enabled
RCV1INTEN Bank 1 receive completion interrupt enable bit
0 Disabled
1 Enabled
RCV0INTEN Bank 0 receive completion interrupt enable bit
0 Disabled
1 Enabled
RCVFININTEN Frame receive completion interrupt enable bit
0 Disabled
1 Enabled
<R>
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