RL78/G1H CHAPTER 18 RF TRANSCEIVER
R01UH0575EJ0120 Rev. 1.20 Page 648 of 920
Dec 22, 2016
(87) Address filter extension address control register (BBADFCON)
PAN coordinator 2 bit is used to set whether PAN coordinator on second address filter side.
Frame pending 2 bit is used to set enable or disable of frame pending for ACK reply on second address filter
side.
First address filter match monitor bit is used to monitor whether the first address matches. The reading
value is corresponding save bank specified by receive data save bank select bit.
Second address filter match monitor bit is used to monitor whether the second address matches. The
reading value is corresponding save bank specified by receive data save bank select bit.
When the address filter extension bit is disabled, values of first and second address filter match monitor bits
are invalid.
When the address filter extension bit is enabled, values of first and second address filter match monitor bits
are invalid under the following conditions.
- Frame version: 00, 01
- Frame type: Beacon frame
- No destination PANID and destination address
- Values of source PANID and PAN identifier register match, or value of PAN identifier register = FFFFH
- PANCORD bit = 0
BBADFCON register is set via serial interface in 8-bit units.
Reset signal generation sets this register to 00H.
Figure 18 - 100 Address Filter Extension Address Control Register (BBADFCON) Format
Caution Be sure to clear bits 4 to 7 to “0”. Bits 2,3 are Read Only.
Address: 010DH After reset: 00H R/W
Symbol76543210
BBADFCON
000
0
ADFMONI2 ADFMONI1 FLMPEND2 PANCORD2
ADFMONI2 Second address filter match monitor bit
0 Not match to second address
1 Match to second address
ADFMONI1 First address filter match monitor bit
0 Not match to first address
1 Match to first address
FLMPEND2 Frame pending 2 bit
0 No frame pending
1 With frame pending
PANCORD2 PAN coordinator 2 bit
0 Not a PAN coordinator
1 PAN coordinator
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