Renesas RL78/G1H

RL78/G1H CHAPTER 18 RF TRANSCEIVER
R01UH0575EJ0120 Rev. 1.20 Page 647 of 920
Dec 22, 2016
Figure 18 - 99 FEC Control Register (BBFECCON) Format
Caution Be sure to set “0” to bit 7. The bit is read as x (undefined).
Address: 010CH After reset: 00H R/W
Symbol76543210
BBFECCON
x MRFSKSFD
FECEN
ACKRCV
FECCON
ACKRCV
FECEN
ACKRTN
FECCON
ACKRTN
FECENTX
FEC
AUTOEN
MRFSKSFD MRFSKSFD select bit
0 phyMRFSKSFD = 0
1 phyMRFSKSFD = 1
FECEN
ACKRCV
FEC enable bit for automatic ACK reception
0 Disable
1 Enable
FECCON
ACKRCV
FEC control bit for automatic ACK reception
0 Regardless of FEC enable bit for automatic ACK reception
1 Depend on FEC enable bit for automatic ACK reception
FECEN
ACKRTN
FEC enable bit for automatic ACK reply
0 Disable
1 Enable
GPIO2DATA
FEC bit
FEC control bit for automatic ACK reply
0 Disables automatic ACK reply
1 Enables automatic ACK reply
FECENTX FEC enable bit for transmission
0 Disable
1 Enable
FECEN
AUTOEN
FEC automatic identification enable bit
0 Disable
1 Enable