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RL78/G1H
CHAPTER 18 RF TRANSCEIVER
R01UH0575EJ0120
Rev
. 1.20
Page 675 of 920
Dec 22, 2016
T
able 18 - 24 Gain Set (Frequ
ency band identifier = 5 to 7) (2/3)
Gain set
0090H
address
Bit [1:0]
0092H
address
Bit [4:0]
00DCH address Bit [4:0]
(00DDH address is set to 19)
00DCH address Bit [4:0]
(00DDH address is set to 25)
00DCH address Bit [7:4]
(00DDH address is set to
1AH)
41
3
0D
1
15
6
42
3
0E
1
15
6
43
3
0F
1
15
6
4
431
0
1
1
5
6
45
3
1
1
1
15
6
4
631
2
1
1
5
6
4
731
3
1
1
5
6
4
831
4
1
1
5
6
4
921
5
1
1
5
6
5
021
6
1
1
5
6
5
121
7
1
1
5
6
5
221
8
1
1
5
6
5
321
9
1
1
5
6
54
2
1A
1
15
6
55
2
1B
1
15
6
56
2
1C
1
15
6
57
2
1D
1
15
6
58
2
1E
1
15
6
59
2
1F
1
15
6
6
030
6
2
1
F
6
6
130
7
2
1
F
6
6
230
8
2
1
F
6
6
330
9
2
1
F
6
64
3
0A
2
1F
6
65
3
0B
2
1F
6
66
3
0C
2
1F
6
67
3
0D
2
1F
6
68
3
0E
2
1F
6
69
3
0F
2
1F
6
7
031
0
2
1
F
6
71
3
1
1
2
1F
6
7
231
2
2
1
F
6
7
331
3
2
1
F
6
7
431
4
2
1
F
6
7
521
5
2
1
F
6
7
621
6
2
1
F
6
7
721
7
2
1
F
6
7
821
8
2
1
F
6
7
921
9
2
1
F
6
80
2
1A
2
1F
6
692
694
Table of Contents
Default Chapter
7
Table of Contents
7
1 Outline
19
Features
19
Ordering Information
22
Pin Configuration (Top View)
24
Pin Identification
25
Block Diagram
26
Outline of Functions
27
2 Connection between Mcu and Rf Transceiver
29
Connection Pins of MCU and RF Transceiver
29
Communication Interface between MCU and RF Transceiver
30
Initial Settings of Unused Internal Pins of MCU
31
Base Operation Clock of RF Unit
32
Power Configuration
33
Peripheral Circuits'connection Diagram
34
3 Pin Functions
37
Port Functions
37
Functions Other than Port Pins
40
Connection of Unused Pins
41
Pin Block Diagrams
42
4 Cpu Architecture
54
Memory Space
54
Internal Program Memory Space
62
Mirror Area
63
Internal Data Memory Space
64
Special Function Register (SFR) Area
64
Extended Special Function Register (2Nd SFR: 2Nd Special Function Register) Area
64
Data Memory Addressing
65
Processor Registers
66
Control Registers
66
General-Purpose Registers
69
ES and CS Registers
70
Special Function Registers (Sfrs)
71
Extended Special Function Registers (2Nd Sfrs: 2Nd Special Function Registers)
77
5 Port Functions
85
Port Configuration
86
Port 0
87
Port 1
87
Port 2
87
Port 3
88
Port 4
88
Port 6
88
Port 7
88
Port 8
88
Port 10
89
Port 13
89
Port 12
90
Port 14
90
Port 15
90
GPIO Port
90
Registers Controlling Port Function
91
Port Mode Registers (Pmxx)
94
Port Registers (Pxx)
96
Pull-Up Resistor Option Registers (Puxx)
98
Port Input Mode Registers (Pimxx)
99
Port Output Mode Registers (Pomxx)
100
Port Mode Control Registers (Pmcxx)
101
A/D Port Configuration Register (ADPC)
102
Port Function Operations
103
Writing to I/O Port
103
Reading from I/O Port
103
Operations on I/O Port
103
Handling Different Potential (1.8 V, 2.5 V, 3 V) by Using I/O Buffers
104
Register Settings When Using Alternate Function
105
Basic Concept When Using Alternate Function
105
Register Settings for Alternate Function Whose Output Function Is Not Used
106
Register Setting Examples for Used Port and Alternate Functions
107
Cautions When Using Port Function
113
Cautions on 1-Bit Manipulation Instruction for Port Register N (Pn)
113
Notes on Specifying the Pin Settings
114
6 Clock Generator
115
Functions of Clock Generator
115
Configuration of Clock Generator
117
Registers Controlling Clock Generator
119
Clock Operation Mode Control Register (CMC)
119
System Clock Control Register (CKC)
122
Clock Operation Status Control Register (CSC)
123
Oscillation Stabilization Time Counter Status Register (OSTC)
124
Oscillation Stabilization Time Select Register (OSTS)
126
Peripheral Enable Registers 0, 1 (PER0, PER1)
128
Subsystem Clock Supply Mode Control Register (OSMC)
132
High-Speed On-Chip Oscillator Frequency Select Register (HOCODIV)
133
High-Speed On-Chip Oscillator Trimming Register (HIOTRM)
134
System Clock Oscillator
135
X1 Oscillator
135
XT1 Oscillator
135
High-Speed On-Chip Oscillator
139
Low-Speed On-Chip Oscillator
139
Clock Generator Operation
140
Controlling Clock
142
Example of Setting High-Speed On-Chip Oscillator
142
Example of Setting X1 Oscillation Clock
144
Example of Setting XT1 Oscillation Clock
146
CPU Clock Status Transition Diagram
147
Condition before Changing CPU Clock and Processing after Changing CPU Clock
153
Time Required for Switchover of CPU Clock and Main System Clock
155
Conditions before Clock Oscillation Is Stopped
156
7 Timer Array Unit
157
Functions of Timer Array Unit
158
Independent Channel Operation Function
158
Simultaneous Channel Operation Function
159
8-Bit Timer Operation Function (Channels 1 and 3 Only)
159
Configuration of Timer Array Unit
160
Timer Count Register Mn (Tcrmn)
164
Timer Data Register Mn (Tdrmn)
166
Registers Controlling Timer Array Unit
167
Peripheral Enable Register 0 (PER0)
168
Timer Clock Select Register M (Tpsm)
169
Timer Mode Register Mn (Tmrmn)
172
Timer Status Register Mn (Tsrmn)
177
Timer Channel Enable Status Register M (Tem)
178
Timer Channel Start Register M (Tsm)
179
Timer Channel Stop Register M (Ttm)
181
Timer Input Select Register 0 (TIS0)
182
Timer Output Enable Register M (Toem)
183
Timer Output Register M (Tom)
184
Timer Output Level Register M (Tolm)
185
Timer Output Mode Register M (Tomm)
186
Noise Filter Enable Register 1 (NFEN1)
187
Registers Controlling Port Functions of Pins to be Used for Timer I/O
189
Basic Rules of Timer Array Unit
190
Basic Rules of Simultaneous Channel Operation Function
190
Basic Rules of 8-Bit Timer Operation Function (Channels 1 and 3 Only)
192
Operation of Counter
193
Count Clock (F TCLK )
193
Start Timing of Counter
195
Operation of Counter
196
Channel Output (Tomn Pin) Control
201
Tomn Pin Output Circuit Configuration
201
Tomn Pin Output Setting
202
Cautions on Channel Output Operation
203
Collective Manipulation of Tomn Bit
208
Timer Interrupt and Tomn Pin Output at Operation Start
209
Timer Input (Timn) Control
210
Timn Input Circuit Configuration
210
Noise Filter
210
Cautions on Channel Input Operation
211
Independent Channel Operation Function of Timer Array Unit
212
Operation as Interval Timer/Square Wave Output
212
Operation as External Event Counter
217
Operation as Input Pulse Interval Measurement
221
Operation as Input Signal High-/Low-Level Width Measurement
225
Operation as Delay Counter
229
Simultaneous Channel Operation Function of Timer Array Unit
233
Operation as PWM Function
233
Cautions When Using Timer Array Unit
240
Cautions When Using Timer Output
240
8 Timer Rj
241
Functions of Timer RJ
241
Configuration of Timer RJ
242
Registers Controlling Timer RJ
243
Peripheral Enable Register 1 (PER1)
244
Subsystem Clock Supply Mode Control Register (OSMC)
245
Timer RJ Counter Register 0 (TRJ0)
246
Timer RJ Control Register 0 (TRJCR0)
247
Timer RJ Mode Register 0 (TRJMR0)
248
Timer RJ Operation
249
Reload Register and Counter Rewrite Operation
249
Timer Mode
250
Coordination with Event Link Controller (ELC)
251
Cautions for Timer RJ
252
Count Operation Start and Stop Control
252
Access to Flags (TUNDF Bit in TRJCR0 Register)
252
Access to Counter Register
252
When Changing Mode
252
When Timer RJ Operating Clock Is Stopped
253
When Count Is Forcibly Stopped by TSTOP Bit
253
When Selecting F IL as Count Source
253
9 Real-Time Clock
254
Functions of Real-Time Clock
254
Configuration of Real-Time Clock
254
Registers Controlling Real-Time Clock
256
Peripheral Enable Register 0 (PER0)
257
Subsystem Clock Supply Mode Control Register (OSMC)
258
Real-Time Clock Control Register 0 (RTCC0)
259
Real-Time Clock Control Register 1 (RTCC1)
260
Second Count Register (SEC)
262
Minute Count Register (MIN)
262
Hour Count Register (HOUR)
263
Day Count Register (DAY)
265
Week Count Register (WEEK)
266
Month Count Register (MONTH)
267
Year Count Register (YEAR)
267
Watch Error Correction Register (SUBCUD)
268
Alarm Minute Register (ALARMWM)
269
Alarm Hour Register (ALARMWH)
269
Alarm Week Register (ALARMWW)
269
Real-Time Clock Operation
271
Starting Operation of Real-Time Clock
271
Shifting to HALT/STOP Mode after Starting Operation
272
Reading/Writing Real-Time Clock
273
Setting Alarm of Real-Time Clock
275
Example of Watch Error Correction of Real-Time Clock
276
10 Bit Interval Timer
279
Functions of 12-Bit Interval Timer
279
Configuration of 12-Bit Interval Timer
279
Registers Controlling 12-Bit Interval Timer
280
Peripheral Enable Register 0 (PER0)
280
Subsystem Clock Supply Mode Control Register (OSMC)
281
12-Bit Interval Timer Control Register (ITMC)
282
12-Bit Interval Timer Operation
283
12-Bit Interval Timer Operation Timing
283
Start of Count Operation and Re-Enter to HALT/STOP Mode after Returned from HALT/STOP Mode
284
11 Clock Output/Buzzer Output Controller
285
Functions of Clock Output/Buzzer Output Controller
285
Configuration of Clock Output/Buzzer Output Controller
287
Registers Controlling Clock Output/Buzzer Output Controller
287
Clock Output Select Registers N (Cksn)
287
Registers Controlling Port Functions of Pins to be Used for Clock or Buzzer Output
289
Operations of Clock Output/Buzzer Output Controller
290
Operation as Output Pin
290
Cautions of Clock Output/Buzzer Output Controller
290
12 Watchdog Timer
291
Functions of Watchdog Timer
291
Configuration of Watchdog Timer
292
Register Controlling Watchdog Timer
293
Watchdog Timer Enable Register (WDTE)
293
Operation of Watchdog Timer
294
Controlling Operation of Watchdog Timer
294
Setting Overflow Time of Watchdog Timer
295
Setting Window Open Period of Watchdog Timer
296
Setting Watchdog Timer Interval Interrupt
297
13 A/D Converter
298
Function of A/D Converter
298
Configuration of A/D Converter
301
Registers Controlling A/D Converter
303
Peripheral Enable Register 0 (PER0)
304
A/D Converter Mode Register 0 (ADM0)
305
A/D Converter Mode Register 1 (ADM1)
313
A/D Converter Mode Register 2 (ADM2)
314
10-Bit A/D Conversion Result Register (ADCR)
316
8-Bit A/D Conversion Result Register (ADCRH)
316
Analog Input Channel Specification Register (ADS)
317
Conversion Result Comparison Upper Limit Setting Register (ADUL)
318
Conversion Result Comparison Lower Limit Setting Register (ADLL)
318
A/D Test Register (ADTES)
319
13.3.11 Registers Controlling Port Function of Analog Input Pins
320
A/D Converter Conversion Operations
321
Input Voltage and Conversion Results
323
A/D Converter Operation Modes
324
Software Trigger Mode (Select Mode, Sequential Conversion Mode)
324
Software Trigger Mode (Select Mode, One-Shot Conversion Mode)
325
Hardware Trigger No-Wait Mode (Select Mode, Sequential Conversion Mode)
326
Hardware Trigger No-Wait Mode (Select Mode, One-Shot Conversion Mode)
327
Hardware Trigger Wait Mode (Select Mode, Sequential Conversion Mode)
328
Hardware Trigger Wait Mode (Select Mode, One-Shot Conversion Mode)
329
A/D Converter Setup Flowchart
330
Setting up Software Trigger Mode
330
Setting up Hardware Trigger No-Wait Mode
331
Setting up Hardware Trigger Wait Mode
332
Setting up Test Mode
333
SNOOZE Mode Function
334
Cautions for A/D Converter
337
14 Serial Array Unit
341
Functions of Serial Array Unit
342
3-Wire Serial I/O (Csip)
342
UART (Uartq)
343
Configuration of Serial Array Unit
344
Shift Register
347
Lower 8 Bits of the Serial Data Register Mn (Sdrmn)
347
Registers Controlling Serial Array Unit
349
Peripheral Enable Register 0 (PER0)
350
Serial Clock Select Register M (Spsm)
351
Serial Mode Register Mn (Smrmn)
353
Serial Communication Operation Setting Register Mn (Scrmn)
354
Serial Data Register Mn (Sdrmn)
357
Serial Flag Clear Trigger Register Mn (Sirmn)
358
Serial Status Register Mn (Ssrmn)
359
Serial Channel Start Register M (Ssm)
361
Serial Channel Stop Register M (Stm)
362
Serial Channel Enable Status Register M (Sem)
363
Serial Output Enable Register M (Soem)
364
Serial Output Register M (Som)
365
Serial Output Level Register M (Solm)
366
Noise Filter Enable Register 0 (NFEN0)
368
14.3.15 Registers Controlling Port Functions of Serial Input/Output Pins
369
Operation Stop Mode
370
Stopping the Operation by Units
370
Stopping the Operation by Channels
371
Operation of 3-Wire Serial I/O (Csip) Communication
372
Master Transmission
374
Master Reception
382
Master Transmission/Reception
390
Slave Transmission
398
Slave Reception
406
Slave Transmission/Reception
412
Calculating Transfer Clock Frequency
420
Procedure for Processing Errors that Occurred During 3-Wire Serial I/O (Csip) Communication
422
Operation of UART (Uartq) Communication
423
UART Transmission
424
UART Reception
433
Calculating Baud Rate
440
Procedure for Processing Errors that Occurred During UART (Uartq) Communication
444
15 Serial Interface Iica
445
Functions of Serial Interface IICA
445
Configuration of Serial Interface IICA
448
Registers Controlling Serial Interface IICA
451
Peripheral Enable Register 0 (PER0)
452
IICA Control Register N0 (Iicctln0)
452
IICA Status Register N (Iicsn)
457
IICA Flag Register N (Iicfn)
459
IICA Control Register N1 (Iicctln1)
461
IICA Low-Level Width Setting Register N (Iicwln)
463
IICA High-Level Width Setting Register N (Iicwhn)
463
Register to Control Port Function of Serial I/O Pin
464
I 2 C Bus Mode Functions
465
Pin Configuration
465
Setting Transfer Clock by Using Iicwln and Iicwhn Registers
466
I 2 C Bus Definitions and Control Methods
468
Start Conditions
468
Addresses
469
Transfer Direction Specification
469
Acknowledge (ACK)
470
Stop Condition
471
Wait
472
Canceling Wait
474
Interrupt Request (Intiican) Generation Timing and Wait Control
475
Address Match Detection Method
476
15.5.10 Error Detection
476
15.5.11 Extension Code
477
15.5.12 Arbitration
478
15.5.13 Wakeup Function
480
Communication Reservation
483
15.5.15 Cautions
487
15.5.16 Communication Operations
488
Timing of I C Interrupt Request (Intiican) Occurrence
496
Timing Charts
517
16 Data Transfer Controller (Dtc)
532
Functions of DTC
532
Configuration of DTC
534
Registers Controlling DTC
535
Allocation of DTC Control Data Area and DTC Vector Table Area
536
Control Data Allocation
537
Vector Table
538
Peripheral Enable Register 1 (PER1)
540
DTC Control Register J (Dtccrj) (J = 0 to 23)
541
DTC Block Size Register J (Dtblsj) (J = 0 to 23)
542
DTC Transfer Count Register J (Dtcctj) (J = 0 to 23)
542
DTC Transfer Count Reload Register J (Dtrldj) (J = 0 to 23)
543
DTC Source Address Register J (Dtsarj) (J = 0 to 23)
543
DTC Destination Address Register J (Dtdarj) (J = 0 to 23)
543
DTC Activation Enable Register I (Dtceni) (I = 0 to 4)
544
DTC Base Address Register (DTCBAR)
547
DTC Operation
547
Activation Sources
548
Normal Mode
549
Repeat Mode
550
Chain Transfers
552
Cautions for DTC
553
Setting DTC Control Data and Vector Table
553
Allocation of DTC Control Data Area and DTC Vector Table Area
553
DTC Pending Instruction
554
Operation When Accessing Data Flash Memory Space
554
Number of DTC Execution Clock Cycles
555
DTC Response Time
556
DTC Activation Sources
556
Operation in Standby Mode Status
557
17 Event Link Controller (Elc)
558
Functions of ELC
558
Configuration of ELC
558
Registers Controlling ELC
559
ELC Operation
561
18 Rf Transceiver
562
RF Transceiver Overview
563
Pin Functions
564
Digital Pin
564
Analog Pin
565
Description of RF Pin Functions
565
Configuration of RF Transceiver
566
Digital Block
566
Analog Block
567
Oscillator Block
568
Power Supply Block
568
Baseband Function
569
Configuration
569
Frame Configuration
570
Index
571
Baseband Interrupt
574
Baseband Function Controlling Register
575
Serial Interface Only for Internal Communication
669
Overview
669
Communication Specification
670
Communication Format
671
RF Mode
673
RF Operating Mode
673
RF Standby Mode
673
State Transition
674
Mode Transition
675
Pin State in each RF Mode
680
Function State in each RF Mode
680
Example of Procedure for Setting
681
Example of Procedure for each Operation
681
Example of Procedure for Function Setting
684
Setting for each Data Rate
712
Notice for Using Baseband Function
722
Notice about Transmission
722
Cautions on First and Second Address Filter Match Monitor Bits
722
19 Interrupt Functions
723
Interrupt Function Types
723
Interrupt Sources and Configuration
723
Registers Controlling Interrupt Functions
727
Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H)
730
Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H)
732
Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H)
734
External Interrupt Rising Edge Enable Registers (EGP0, EGP1), External Interrupt Falling Edge Enable Registers (EGN0, EGN1)
736
Program Status Word (PSW)
738
Interrupt Servicing Operations
739
Maskable Interrupt Request Acknowledgment
739
Software Interrupt Request Acknowledgment
742
Multiple Interrupt Servicing
742
Interrupt Servicing During Division Instruction
746
Interrupt Request Hold
748
20 Standby Function
749
Registers Controlling Standby Function
750
Standby Function Operation
751
STOP Mode
756
SNOOZE Mode
761
21 Reset Function
764
Timing of Reset Operation
766
Register for Confirming Reset Source
770
22 Power-On-Reset Circuit
773
Configuration of Power-On-Reset Circuit
774
23 Voltage Detector
778
Configuration of Voltage Detector
779
Voltage Detection Register (LVIM)
780
Voltage Detection Level Register (LVIS)
781
Operation of Voltage Detector
782
When Used as Interrupt Mode
784
When Used as Interrupt and Reset Mode
786
Cautions for Voltage Detector
791
24 Safety Functions
793
Registers Used by Safety Functions
794
CRC Operation Function (General-Purpose CRC)
798
RAM Parity Error Detection Function
801
RAM Guard Function
803
SFR Guard Function
804
Invalid Memory Access Detection Function
805
Frequency Detection Function
807
A/D Test Function
809
Digital Output Signal Level Detection Function for I/O Pins
813
25 Regulator
814
26 Option Byte
815
On-Chip Debug Option Byte (000C3H/ 010C3H)
816
Format of User Option Byte
817
Format of On-Chip Debug Option Byte
823
Flash Memory
824
27 Flash Memory
825
Serial Programming Using Flash Memory Programmer
825
Programming Environment
826
Connection of Pins on Board
828
Port Pins
829
Programming Method
830
Flash Memory Programming Mode
831
Selecting Communication Mode
833
Communication Commands
834
Processing Time for each Command When PG-FP5 Is in Use (Reference Value)
835
Self-Programming
836
Self-Programming Procedure
837
Boot Swap Function
838
Flash Shield Window Function
840
Security Settings
841
Data Flash
843
Register Controlling Data Flash Memory
844
Procedure for Accessing Data Flash Memory
845
28 On-Chip Debug Function
846
On-Chip Debug Security ID
847
29 Bcd Correction Circuit
849
BCD Correction Circuit Operation
850
30 Instruction Set
852
Conventions Used in Operation List
853
Description of Operation Column
854
Description of Flag Operation Column
855
Operation List
856
31 Electrical Specifications
874
Absolute Maximum Ratings
875
Oscillator Characteristics
877
DC Characteristics
878
Supply Current Characteristics
883
AC Characteristics
888
Peripheral Functions Characteristics
893
Serial Interface IICA
909
Analog Characteristics
912
POR Characteristics
913
LVD Characteristics
914
Power Supply Voltage Rising Slope Characteristics
915
RF Transceiver Characteristics
916
DC Characteristics
918
Transceiver Reception Characteristics
919
Transceiver Transmission Characteristics
920
Ieee802.15.4G Frequency/Data Rate Table
921
AC Characteristics
922
RAM Data Retention Characteristics
925
Timing for Switching Flash Memory Programming Modes
926
32 Package Drawing
927
Appendix A Revision History
928
A.2 Revision History of Preceding Editions
930
5
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Renesas RL78/G1H Specifications
General
Brand
Renesas
Model
RL78/G1H
Category
Microcontrollers
Language
English
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