RL78/G1H CHAPTER 20 STANDBY FUNCTION
R01UH0575EJ0120 Rev. 1.20 Page 739 of 920
Dec 22, 2016
Remark Operation stopped: Operation is automatically stopped before switching to the STOP mode.
Operation disabled: Operation is stopped before switching to the STOP mode.
f
IH: High-speed on-chip oscillator clock fIL: Low-speed on-chip oscillator clock
fX: X1 clock fEX: External main system clock
fXT: XT1 clock fEXS: External subsystem clock
Table 20 - 3 Operating Statuses in STOP Mode
STOP Mode Setting
Item
When STOP Instruction is Executed While CPU is Operating on Main System Clock
When CPU is Operating on
High-speed On-chip
Oscillator Clock (f
IH)
When CPU is Operating
on X1 Clock (f
X)
When CPU is Operating on
External Main System Clock
(f
EX)
System clock Clock supply to the CPU is stopped
Main system
clock
f
IH Stopped
f
X
fEX
Subsystem
clock
fXT Status before STOP mode was set is retained
f
EXS
fIL Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and
WUTMMCK0 bit of subsystem clock supply mode control register (OSMC)
• WUTMMCK0 = 1: Oscillates
• WUTMMCK0 = 0 and WDTON = 0: Stops
• WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 1: Oscillates
• WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 0: Stops
CPU Operation stopped
Code flash memory
Data flash memory
RAM
Port (latch) Status before STOP mode was set is retained
Timer array unit Operation disabled
Real-time clock (RTC) Operable
12-bit Interval timer
Watchdog timer See
CHAPTER 12 WATCHDOG TIMER.
Timer RJ • Operable when the subsystem clock is selected as the count source and RTCLPC in
the OSMC register = 0
• Operable when the low-speed on-chip oscillator is selected as the count source
• Operation is disabled under any conditions other than the above
Clock output/buzzer output Operates when the subsystem clock is selected as the clock source for counting and
the RTCLPC bit is 0 (operation is disabled when a clock other than the subsystem
clock is selected and the RTCLPC bit is not 0).
A/D converter Wakeup operation is enabled (switching to SNOOZE mode)
Serial array unit (SAU) Operation disabled
Serial interface (IICA) Wakeup by address match operable
Data transfer controller (DTC) DTC activation source receiving operation enabled (switching to SNOOZE mode)
Event link controller (ELC) Operable function blocks can be linked
Power-on-reset function Operable
Voltage detection function
External interrupt
CRC operation
function
High-speed CRC Operation stopped
General-purpose CRC
Illegal-memory access detection function
RAM parity error detection function
RAM guard function
SFR guard function
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