Renesas RL78/G1H User Manual

RL78/G1H CHAPTER 30 INSTRUCTION SET
R01UH0575EJ0120 Rev. 1.20 Page 843 of 920
Dec 22, 2016
Note 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no
data is accessed.
Note 2. Number of CPU clocks (f
CLK) when the code flash memory is accessed, or when the data flash memory is accessed by
an 8-bit instruction.
Note 3. Except rp = AX
Note 4. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the
internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Table 30 - 10 Operation List (6/18)
Instruction
Group
Mnemonic Operands Bytes
Clocks
Clocks
Flag
Note 1 Note 2
ZACCY
16-bit data
transfer
MOVW BC, !addr16
314
BC
←
(addr16)
BC, ES:!addr16
425
BC
←
(ES, addr16)
DE, !addr16
314
DE
←
(addr16)
DE, ES:!addr16
425
DE
←
(ES, addr16)
HL, !addr16
314
HL
←
(addr16)
HL, ES:!addr16
425
HL
←
(ES, addr16)
BC, saddrp
21—
BC
←
(saddrp)
DE, saddrp
21—
DE
←
(saddrp)
HL, saddrp
21—
HL
←
(saddrp)
XCHW
AX, rp
Note 3
11—
AX
←→
rp
ONEW AX
11—
AX
←
0001H
BC
11—
BC
←
0001H
CLRW AX
11—
AX
←
0000H
BC
11—
BC
←
0000H
8-bit
operation
ADD A, #byte
21—
A, CY
←
A + byte
×××
saddr, #byte
32—
(saddr), CY
←
(saddr) + byte
×××
A, r
Note 4
21—
A, CY
←
A + r
×××
r, A
21—
r, CY
←
r + A
×××
A, !addr16
314
A, CY
←
A + (addr16)
×××
A, ES:!addr16
425
A, CY
←
A + (ES, addr16)
×××
A, saddr
21—
A, C
←
A + (saddr)
×××
A, [HL]
114
A, CY
←
A + (HL)
×××
A, ES:[HL]
225
A,CY
←
A + (ES, HL)
×××
A, [HL+byte]
214
A, CY
←
A + (HL + byte)
×××
A, ES:[HL+byte]
325
A,CY
←
A + ((ES, HL) + byte)
×××
A, [HL+B]
214
A, CY
←
A + (HL + B)
×××
A, ES:[HL+B]
325
A,CY
←
A + ((ES, HL) + B)
×××
A, [HL+C]
214
A, CY
←
A + (HL + C)
×××
A, ES:[HL+C]
325
A,CY
←
A + ((ES, HL) + C)
×××

Renesas RL78/G1H Specifications

General

Brand	Renesas
Model	RL78/G1H
Category	Microcontrollers
Language	English