RL78/G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS
R01UH0575EJ0120 Rev. 1.20 Page 885 of 920
Dec 22, 2016
Note 1. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 2. Use it with VDD ≥ Vb.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin
and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For V
IH and
V
IL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output)
(T
A = -40 to +85 °C, 1.8 V ≤ VDD ≤ 3.6 V, VSS = 0 V) (3/3)
Parameter Symbol Conditions HS (high-speed main)
mode
LS (low-speed main)
mode
Unit
MIN. MAX. MIN. MAX.
SIp setup time
(to SCKp↓)
Note 1
tSIK1 2.7 V ≤ VDD < 3.6 V,
2.3 V
≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
44 110 ns
1.8 V
≤ VDD < 3.3 V,
1.6 V
≤ Vb ≤ 2.0 V
Note 2
,
Cb = 30 pF, Rb = 5.5 kΩ
110 110 ns
SIp hold time
(from SCKp↓)
Note 1
tKSI1 2.7 V ≤ VDD < 3.6 V,
2.3 V
≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
19 19 ns
1.8 V
≤ VDD < 3.3 V,
1.6 V
≤ Vb ≤ 2.0 V
Note 2
,
Cb = 30 pF, Rb = 5.5 k
Ω
19 19 ns
Delay time from SCKp↑
to SOp output
Note 1
tKSO1 2.7 V ≤ VDD < 3.6 V,
2.3 V
≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
25 25 ns
1.8 V
≤ VDD < 3.3 V,
1.6 V
≤ Vb ≤ 2.0 V
Note 2
,
Cb = 30 pF, Rb = 5.5 kΩ
25 25 ns
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