Sel 751A - Page 615

J.13
Date Code 20100129 Instruction Manual SEL-751A Relay
Relay Word Bits
Definitions
T04_LED Asserts when the SELOGIC control equation T04_LED result is logical 1 (see Table 4.66). 34
T05_LED Asserts when the SEL
OGIC control equation T05_LED result is logical 1 (see Table 4.66). 34
T06_LED Asserts when the SEL
OGIC control equation T06_LED result is logical 1 (see Table 4.66). 34
TLED_01 Front-Panel T01_LED. 0
TLED_02 Front-Panel T02_LED. 0
TLED_03 Front-Panel T03_LED. 0
TLED_04 Front-Panel T04_LED. 0
TLED_05 Front-Panel T05_LED. 0
TLED_06 Front-Panel T06_LED. 0
TMB1A to TMB8A Channel A transmit M
IRRORED BITS TMB1A through TMB8A. 89
TMB1B to TMB8B Channel B transmit M
IRRORED BITS TMB1B through TMB8B. 91
TOL1 Arc-Flash light input 1 element pickup. 116
TOL2 Arc-Flash light input 2 element pickup. 116
TOL3 Arc-Flash light input 3 element pickup. 116
TOL4 Arc-Flash light input 4 element pickup. 116
TQUAL1 Time Quality Bit, add 1 when asserted (synchrophasors). 112
TQUAL2 Time Quality Bit, add 2 when asserted (synchrophasors). 112
TQUAL4 Time Quality Bit, add 4 when asserted (synchrophasors). 112
TQUAL8 Time Quality Bit, add 8 when asserted (synchrophasors). 112
TR Trip SEL
OGIC control equation (see Figure 4.1). 29
TREA1 Trigger Reason for Bit 1 for Synchrophasors (see Table H . 7). 31
TREA2 Trigger Reason for Bit 2 for Synchrophasors (see Table H . 7). 31
TREA3 Trigger Reason for Bit 3 for Synchrophasors (see Table H . 7). 31
TREA4 Trigger Reason for Bit 4 for Synchrophasors (see Table H . 7). 31
TRGTR Target Reset. Asserts for one quarter-cycle when you execute a front-panel, serial port target reset
command, or Modbus target reset.
22
TRIP Output of Trip Logic (see Figure 4.29). 15
TRIP_LED Front-Panel TRIP LED. 0
TSOK Assert if current time source accuracy is sufficient for synchronized phasor measurements. (Refer
to Table H . 8.)
13
TUTCS Offset hours sign from UTC time, subtract the UTC offset if TUTCS is asserted; otherwise, add.
(Synchrophasors)
113
TUTC1 Offset hours from UTC time, binary, add 1 if asserted 113
TUTC2 Offset hours from UTC time, binary, add 2 if asserted 113
TUTC4 Offset hours from UTC time, binary, add 4 if asserted 113
TUTC8 Offset hours from UTC time, binary, add 8 if asserted 113
TUTCH Offset half-hour from UTC time, binary, add 0.5 if asserted 113
ULCL Unlatch close conditions SEL
OGIC equation state (see Table 4.25). 34
ULTRIP Unlatch (auto reset) trip from SEL
OGIC control equation (see Table 4.25). 29
VBxxx Virtual bits used for incoming GOOSE messages (xxx = 001 to 128) (see Virtual Bits description
on page F.5).
93–108
Table J.2 Relay Word Bit Definitions for the SEL-751A (Sheet 10 of 11)
Bit Definition Row