LL_TIM_ONEPULSEMODE_SINGLE
Counter is not stopped at update event
LL_TIM_ONEPULSEMODE_REPETITIVE
Counter stops counting at the next update
event
OSSI
When inactive, OCx/OCxN outputs are disabled
When inactive, OxC/OCxN outputs are first forced with their
inactive level then forced to their idle level after the deadtime
OSSR
When inactive, OCx/OCxN outputs are disabled
When inactive, OC/OCN outputs are enabled with their
inactive level as soon as CCxE=1 or CCxNE=1
Slave Mode
LL_TIM_SLAVEMODE_DISABLED
Reset Mode - Rising edge of the selected trigger
input (TRGI) reinitializes the counter
Gated Mode - The counter clock is enabled when the
trigger input (TRGI) is high
Trigger Mode - The counter starts at a rising edge of
the trigger TRGI
TIM11 External Input Capture 1 Remap
LL_TIM_TIM11_TI1_RMP_GPIO
TIM11 channel 1 is connected to GPIO
LL_TIM_TIM11_TI1_RMP_GPIO1
TIM11 channel 1 is connected to GPIO
LL_TIM_TIM11_TI1_RMP_GPIO2
TIM11 channel 1 is connected to GPIO
LL_TIM_TIM11_TI1_RMP_HSE_RTC
TIM11 channel 1 is connected to HSE_RTC
TIM2 Internal Trigger1 Remap TIM8
LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
TIM2_ITR1 is connected to TIM8_TRGO
LL_TIM_TIM2_ITR1_RMP_ETH_PTP
TIM2_ITR1 is connected to ETH_PTP
LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
TIM2_ITR1 is connected to OTG_FS SOF
LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF
TIM2_ITR1 is connected to OTG_HS SOF
TIM5 External Input Ch4 Remap
TIM5 channel 4 is connected to GPIO
TIM5 channel 4 is connected to LSI internal clock
TIM5 channel 4 is connected to LSE
TIM5 channel 4 is connected to RTC wakeup interrupt
Trigger Output
UG bit from the TIMx_EGR register is used as trigger output
Counter Enable signal (CNT_EN) is used as trigger output
Update event is used as trigger output
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