ST STM32F2 User Manual

HAL RCC Generic Driver
UM1940
450/1371
DocID028236 Rev 2
Macro to configure the main PLL clock source,
multiplication and division factors.
Parameters:
__RCC_PLLSource__: specifies the PLL entry clock
source. This parameter can be one of the following
values:
RCC_PLLSOURCE_HSI: HSI oscillator clock
selected as PLL clock entry
RCC_PLLSOURCE_HSE: HSE oscillator clock
selected as PLL clock entry
__PLLM__: specifies the division factor for PLL VCO
input clock This parameter must be a number between
Min_Data = 2 and Max_Data = 63.
__PLLN__: specifies the multiplication factor for PLL
VCO output clock This parameter must be a number
between Min_Data = 192 and Max_Data = 432.
__PLLP__: specifies the division factor for main
system clock (SYSCLK) This parameter must be a
number in the range {2, 4, 6, or 8}.
__PLLQ__: specifies the division factor for OTG FS,
SDIO and RNG clocks This parameter must be a
number between Min_Data = 2 and Max_Data = 15.
Notes:
This function must be used only when the main PLL is
disabled.
This clock source (RCC_PLLSource) is common for
the main PLL and PLLI2S.
You have to set the PLLM parameter correctly to
ensure that the VCO input frequency ranges from 1 to
2 MHz. It is recommended to select a frequency of 2
MHz to limit PLL jitter.
You have to set the PLLN parameter correctly to
ensure that the VCO output frequency is between 192
and 432 MHz.
If the USB OTG FS is used in your application, you
have to set the PLLQ parameter correctly to have 48
MHz clock for the USB. However, the SDIO and RNG
need a frequency lower than or equal to 48 MHz to
work correctly.
PLL I2S Configuration
__HAL_RCC_PLLI2S_ENABLE
Notes:
The PLLI2S is disabled by hardware when entering
STOP and STANDBY modes.
__HAL_RCC_PLLI2S_DISABLE
__HAL_RCC_PLLI2S_CONFIG
Description:
Macro to configure the PLLI2S clock multiplication
and division factors .

ST STM32F2 Specifications

General

Brand	ST
Model	STM32F2
Category	Microcontrollers
Language	English