ST STM32F2 - Page 623

UM1940
HAL TIM Generic Driver
DocID028236 Rev 2
623/1371
When the USR bit of the TIMx_CR1
register is reset, any of the following events
generate an update interrupt or DMA
request (if enabled): _ Counter
overflow/underflow _ Setting the UG bit _
Update generation through the slave mode
controller
__HAL_TIM_SET_CAPTUREPOLARIT
Y
Description:
Sets the TIM Capture x input polarity on
runtime.
Parameters:
__HANDLE__: TIM handle.
__CHANNEL__: TIM Channels to be
configured. This parameter can be one of
the following values:
TIM_CHANNEL_1: TIM Channel 1
selected
TIM_CHANNEL_2: TIM Channel 2
selected
TIM_CHANNEL_3: TIM Channel 3
selected
TIM_CHANNEL_4: TIM Channel 4
selected
__POLARITY__: Polarity for TIx source
TIM_INPUTCHANNELPOLARITY_RIS
ING: Rising Edge
TIM_INPUTCHANNELPOLARITY_FA
LLING: Falling Edge
TIM_INPUTCHANNELPOLARITY_BO
THEDGE: Rising and Falling Edge
Return value:
None
Notes:
The polarity
TIM_INPUTCHANNELPOLARITY_BOTHE
DGE is not authorized for TIM Channel 4.
TIM Flag definition
TIM_FLAG_UPDATE
TIM_FLAG_CC1
TIM_FLAG_CC2
TIM_FLAG_CC3
TIM_FLAG_CC4
TIM_FLAG_COM
TIM_FLAG_TRIGGER
TIM_FLAG_BREAK