LL_ADC_SAMPLINGTIME_84CYCLES
Sampling time 84 ADC clock cycles
LL_ADC_SAMPLINGTIME_112CYCLES
Sampling time 112 ADC clock cycles
LL_ADC_SAMPLINGTIME_144CYCLES
Sampling time 144 ADC clock cycles
LL_ADC_SAMPLINGTIME_480CYCLES
Sampling time 480 ADC clock cycles
ADC common - Clock source
LL_ADC_CLOCK_SYNC_PCLK_DIV2
ADC synchronous clock derived from AHB clock
with prescaler division by 2
LL_ADC_CLOCK_SYNC_PCLK_DIV4
ADC synchronous clock derived from AHB clock
with prescaler division by 4
LL_ADC_CLOCK_SYNC_PCLK_DIV6
ADC synchronous clock derived from AHB clock
with prescaler division by 6
LL_ADC_CLOCK_SYNC_PCLK_DIV8
ADC synchronous clock derived from AHB clock
with prescaler division by 8
ADC common - Measurement path to internal channels
LL_ADC_PATH_INTERNAL_NONE
ADC measurement pathes all disabled
LL_ADC_PATH_INTERNAL_VREFINT
ADC measurement path to internal channel
VrefInt
LL_ADC_PATH_INTERNAL_TEMPSENSOR
ADC measurement path to internal channel
temperature sensor
LL_ADC_PATH_INTERNAL_VBAT
ADC measurement path to internal channel
Vbat
ADC instance - Data alignment
ADC conversion data alignment: right aligned (alignment
on data register LSB bit 0)
ADC conversion data alignment: left aligned (aligment
on data register MSB bit 15)
ADC flags
ADC flag ADC group regular conversion start
ADC flag ADC group regular end of unitary conversion or
sequence conversions (to configure flag of end of
conversion, use function
ADC flag ADC group regular overrun
ADC flag ADC group injected conversion start
ADC flag ADC group injected end of sequence
conversions (Note: on this STM32 serie, there is no flag
ADC group injected end of unitary conversion. Flag noted
as "JEOC" is corresponding to flag "JEOS" in other
STM32 families)
ADC flag ADC analog watchdog 1
ADC flag ADC multimode master group regular end of
unitary conversion or sequence conversions (to configure
flag of end of conversion, use function
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