ST STM32F2

UM1940
LL ADC Generic Driver
DocID028236 Rev 2
771/1371
LL_ADC_MULTI_DUAL_INJ_ALTERN
ADC dual mode enabled: group injected
alternate trigger. Works only with external
triggers (not internal SW start)
LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
ADC dual mode enabled: Combined
group regular simultaneous + group
injected simultaneous
LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
ADC dual mode enabled: Combined
group regular simultaneous + group
injected alternate trigger
LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
ADC dual mode enabled: Combined
group regular interleaved + group
injected simultaneous
LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
ADC triple mode enabled: Combined
group regular simultaneous + group
injected simultaneous
LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
ADC triple mode enabled: Combined
group regular simultaneous + group
injected alternate trigger
LL_ADC_MULTI_TRIPLE_INJ_SIMULT
ADC triple mode enabled: group injected
simultaneous
LL_ADC_MULTI_TRIPLE_REG_SIMULT
ADC triple mode enabled: group regular
simultaneous
LL_ADC_MULTI_TRIPLE_REG_INTERL
ADC triple mode enabled: Combined
group regular interleaved
LL_ADC_MULTI_TRIPLE_INJ_ALTERN
ADC triple mode enabled: group injected
alternate trigger. Works only with external
triggers (not internal SW start)
Multimode - Delay between two sampling phases
LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
ADC multimode delay between two
sampling phases: 5 ADC clock cycles
LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
ADC multimode delay between two
sampling phases: 6 ADC clock cycles
LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
ADC multimode delay between two
sampling phases: 7 ADC clock cycles
LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
ADC multimode delay between two
sampling phases: 8 ADC clock cycles
LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
ADC multimode delay between two
sampling phases: 9 ADC clock cycles
LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
ADC multimode delay between two
sampling phases: 10 ADC clock cycles
LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
ADC multimode delay between two
sampling phases: 11 ADC clock cycles
LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
ADC multimode delay between two
sampling phases: 12 ADC clock cycles
LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
ADC multimode delay between two