sampling phases: 13 ADC clock cycles
LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
ADC multimode delay between two
sampling phases: 14 ADC clock cycles
LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
ADC multimode delay between two
sampling phases: 15 ADC clock cycles
LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
ADC multimode delay between two
sampling phases: 16 ADC clock cycles
LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
ADC multimode delay between two
sampling phases: 17 ADC clock cycles
LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
ADC multimode delay between two
sampling phases: 18 ADC clock cycles
LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
ADC multimode delay between two
sampling phases: 19 ADC clock cycles
LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
ADC multimode delay between two
sampling phases: 20 ADC clock cycles
ADC registers compliant with specific purpose
LL_ADC_DMA_REG_REGULAR_DATA
LL_ADC_DMA_REG_REGULAR_DATA_MULTI
ADC group regular - Continuous mode
ADC conversions are performed in single mode:
one conversion per trigger
LL_ADC_REG_CONV_CONTINUOUS
ADC conversions are performed in continuous
mode: after the first trigger, following conversions
launched successively automatically
ADC group regular - DMA transfer of ADC conversion data
LL_ADC_REG_DMA_TRANSFER_NONE
ADC conversions are not transferred by
DMA
LL_ADC_REG_DMA_TRANSFER_LIMITED
ADC conversion data are transferred by
DMA, in limited mode (one shot mode):
DMA transfer requests are stopped
when number of DMA data transfers
(number of ADC conversions) is
reached. This ADC mode is intended to
be used with DMA mode non-circular.
LL_ADC_REG_DMA_TRANSFER_UNLIMITED
ADC conversion data are transferred by
DMA, in unlimited mode: DMA transfer
requests are unlimited, whatever number
of DMA data transferred (number of
ADC conversions). This ADC mode is
intended to be used with DMA mode
circular.
ADC group regular - Flag EOC selection (unitary or sequence conversions)
LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
ADC flag EOC (end of unitary
conversion) selected
LL_ADC_REG_FLAG_EOC_UNITARY_CONV
ADC flag EOS (end of sequence