Introduction
18 Design Guide
Flight Time Flight time is a term in the timing equation that includes the signal propagation
delay, any effects the system has on the Tco of the driver, plus any adjustments
to the signal at the receiver needed to guarantee the setup time of the receiver.
More precisely, flight time is defined as:
• The time difference between a signal at the input pin of a receiving agent
crossing the switching voltage (adjusted to meet the receiver manufacturer’s
conditions required for AC timing specifications; i.e., ringback, etc.) and the
output pin of the driving agent crossing the switching voltage when the driver
is driving a test load used to specify the driver’s AC timings.
• Maximum and Minimum Flight Time – Flight time variations are caused by
many different parameters. The more obvious causes include variation of
the board dielectric constant, changes in load condition, crosstalk, power
noise, variation in termination resistance, and differences in I/O buffer
performance as a function of temperature, voltage, and manufacturing
process. Some less obvious causes include effects of Simultaneous
Switching Output (SSO) and packaging effects.
• Maximum flight time is the largest acceptable flight time that a network
experiences under all conditions.
• Minimum flight time is the smallest acceptable flight time that a network
experiences under all conditions.
Full-power During full-power operation, all components on the motherboard remain
powered. Note that full-power operation includes both the full-on operating state,
and the S1 (processor stop-grant) state.
GTLREF Reference voltage for AGTL+ input pins.
Inter-Symbol
Interference (ISI)
The effect of a previous signal (or transition) on the interconnect delay. For
example, when a signal is transmitted down a line, and the reflections due to the
transition have not completely dissipated, the following data transition launched
onto the bus is affected. ISI is dependent upon frequency, time delay of the line,
and the reflection coefficient at the driver and receiver. ISI can impact both timing
and signal integrity.
Network The network is the trace of a Printed Circuit Board (PCB) that completes an
electrical connection between two or more components.
Overshoot The maximum voltage observed for a signal at the device pad, measured with
respect to VCC.
Pad The electrical contact point of a semiconductor die to the package substrate. A
pad is only observable in simulations.
Pin The contact point of a component package to the traces on a substrate, such as
the motherboard. Signal quality and timings can be measured at the pin.
Power-Good “Power-Good,” “PWRGOOD,” or “CPUPWRGOOD” (an active high signal)
indicates that all of the system power supplies and clocks are stable.
PWRGOOD should go active a predetermined time after system voltages are
stable and should go inactive as soon as any of these voltages fail their
specifications.
Power Rails A power supply has five power rails: +12 V, –12 V, +5 V, +3.3 V, and +5 VSB. In
addition to these power rails from the power supply, several other power rails are
created by voltage regulators on the Reference Board.
Ringback The voltage to which a signal changes after reaching its maximum absolute
value. Ringback may be caused by reflections, driver oscillations, or other
transmission line phenomena.
System Bus The System Bus is the bus which connects the processor to the platform.
Setup Window The time between the beginning of Setup to Clock (TSU_MIN) and the arrival of
a valid clock edge. This window may be different for each type of bus agent in
the system.
Convention/Terminology Description
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