EasyManuals Logo

Intel Xeon User Manual

Intel Xeon
305 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #194 background imageLoading...
Page #194 background image
Schematic Checklist
194 Design Guide
Hub Interface A
HI[11:0] Maximum length of 20" (stripline routing). Refer to Section 7.3.1.
HI_STBF
11
HI_STBS
11
Connect to ICH3-S.
Must NOT have pull-up, pull-down, or series
resistors.
Refer to Section 7.3.1.
Hub Interface B, C, D
HI[18:0]
HI[21:20]
Maximum length of 20" (stripline routing). Refer to Section 7.2.1.
PSTRBF
PSTRBS
PUSTRBF
PUSTRBS
Connect to P64H2.
•Must
not have pull-up, pull-down, or series
resistors.
Refer to Section 7.2.
Clocks, Reset, Miscellaneous Signals
HCLKINP
HLCKINN
Route with a 49.9 ± 1% pull-down resistor to
ground.
Refer to Section 4.1.1.
CLK66 Place 43
series resistor close to CK408B. Refer to Section 4.1.2.
RSTIN# Connect to PCIRST# output of the ICH3-S.
Miscellaneous Signals
XORMODE# 4.7 k ± 5% pull-up to VCC_3.3. Required for normal
operation.
Reserved
(Ball B30)
•4.7 k
± 5% pull-up to VCC_3.3. Required for normal
operation.
Reserved
(Ball D29)
•1 k
± 5% pull-down to Ground. Required for normal
operation.
HIRCOMP_A Tie the MCH RCOMP pin to a 24.9
± 1% pull-
up to VCC_1.2
(For Trace Impedance = 50
± 10%).
Used to calibrate the I/O
Buffers.
Resistive compensation is
used by the ICH3-S and MCH
to adjust the buffer
characteristics to specific
board characteristic.
Refer to Section 7.3.3.
HIRCOMP_B
HIRCOMP_C
HIRCOMP_D
Tie the MCH RCOMP pins to a 24.9
± 1%
pull-up to VCC_1.2
(For trace impedance = 50
± 10%).
Tie the P64H2 RCOMP pins to a 61.9
± 1%
pull-up to VCC_1.8
(For trace impedance = 50
± 10%).
Used to calibrate the I/O
Buffers.
Resistive compensation is
used by the P64H2 and MCH
to adjust the buffer
characteristics to specific
board characteristics.
Refer to Section 7.2.3.
HXRCOMP
HYRCOMP
Tie each COMP pin to a 25
± 1% pull-down
resistor to ground.
This signal is used to calibrate
the Host AGTL+ I/O buffer
characteristics to specific
board characteristics.
Refer to Section 5.3.5.
Table 13-2. MCH Schematic Checklist (Sheet 2 of 3)
Checklist Items Recommendations Comments

Table of Contents

Other manuals for Intel Xeon

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Intel Xeon and is the answer not in the manual?

Intel Xeon Specifications

General IconGeneral
BrandIntel
ModelXeon
CategoryProcessor
LanguageEnglish

Related product manuals