Intel Xeon User Manual

Design Guide 9
Figures
1-1 Example Intel® Xeon™ Processor with 512 KB L2 Cache / Intel® E7500 Chipset
Based System Configuration23
2-1 Intel® Xeon™ Processor with 512 KB L2 Cache Quadrant Layout (Top View)..26
2-2 Intel
®
E7500 MCH Quadrant Layout (Top View).................................................27
2-3 Intel
®
ICH3-S Quadrant Layout (Top View) ........................................................28
2-4 Intel
®
P64H2 Quadrant Layout (Top View) .........................................................29
3-1 Intel® E7500 Chipset Customer Reference Board System Placement Example32
3-2 8 Layer, 50 Ω Board with 5 mil Traces................................................................33
4-1 Intel® E7500 Chipset-Based System Clocking Diagram.....................................37
4-2 Source Shunt Termination...................................................................................38
4-3 Clock Skew As Measured from Agent to Agent ..................................................40
4-4 Trace Spacing for HOST_CLK Clocks ................................................................40
4-5 Stuffing Options for CK408 and CK408B ............................................................41
4-6 Topology for CLK66 ............................................................................................42
4-7 Clock Skew Requirements ..................................................................................43
4-8 Example of Adding a Single Connector...............................................................44
4-9 Example of Adding Two Connectors and/or a Riser ...........................................44
4-10 Topology for CLK33_ICH3-S...............................................................................45
4-11 Topology for CLK33 to PCI Device Down ...........................................................46
4-12 Topology for CLK33 to PCI Slot ..........................................................................47
4-13 Topology for CLK14 ............................................................................................48
4-14 Topology for USB_CLK.......................................................................................49
4-15 Decoupling Capacitors Placement and Connectivity ..........................................50
5-1 Dual Processor System Bus Topology................................................................54
5-2 Trace Length Matching for the Dual Processor System Bus...............................57
5-3 RESET# Topology...............................................................................................59
5-4 Topology for Asynchronous GTL+ Signals Driven by the Processor ..................60
5-5 Recommended THERMTRIP# Circuit.................................................................61
5-6 Topology for Asynchronous GTL+ Signals Driven by the Chipset ......................61
5-7 Topology for PWRGOOD (CPUPWRGOOD)......................................................62
5-8 INIT# Routing Topology ......................................................................................62
5-9 Voltage Translator Circuit....................................................................................63
5-10 BR[3:0]# Connection for DP Configuration..........................................................64
6-1 4 DIMM per Channel Implementation..................................................................68
6-2 3 DIMM per Channel Implementation..................................................................68
6-3 Trace Width and Spacing for All DDR Signals Except CMDCLK/CMDCLK#......69
6-4 Source Synchronous Topology ...........................................................................71
6-5 Trace Length Matching Requirements for Source Synchronous Routing ...........72
6-6 DQS To CMDCLK Pair Length Matching ............................................................72
6-7 Command Clock Topology..................................................................................73
6-8 Trace Width/Spacing for CMDCLK/CMDCLK# Routing......................................74
6-9 Length Matching Requirements for Source Clocked Signal, CKE, and CS[7:0]#74
6-10 Source Clocked Signal Topology ........................................................................75
6-11 Chip Select Topology ..........................................................................................76
6-12 CKE Topology .....................................................................................................77
6-13 Receive Enable Signal Routing Guidelines.........................................................78
6-14 DDRCOMP Resistive Compensation..................................................................79
6-15 DDRCVOL and DDRCVOH Resistive Compensation.........................................79

Intel Xeon Specifications

General

Brand	Intel
Model	Xeon
Category	Processor
Language	English