dsPIC30F Family Reference Manual
DS70053C-page 6-8 © 2004 Microchip Technology Inc.
6.2.2.2 Oscillator Failure Trap (Hard Trap, Level 14)
An oscillator failure trap event will be generated for any of the following reasons:
• The Fail-Safe Clock Monitor (FSCM) is enabled and has detected a loss of the system
clock source.
• A loss of PLL lock has been detected during normal operation using the PLL.
• The FSCM is enabled and the PLL fails to achieve lock at a Power-On Reset (POR).
An oscillator failure trap event can be detected in software by polling the OSCFAIL status bit
(INTCON1<1>), or the CF status bit (OSCCON<3>). To avoid re-entering the Trap Service
Routine, the OSCFAIL status flag must be cleared in software prior to returning from the trap with
a RETFIE instruction.
Refer to Section 7. “Oscillator” and Section 24. “Device Configuration” for more information
about the FSCM.
6.2.2.3 Address Error Trap (Hard Trap, Level 13)
The following paragraphs describe operating scenarios that would cause an address error trap
to be generated:
1. A misaligned data word fetch is attempted. This condition occurs when an instruction
performs a word access with the LSb of the effective address set to ‘1’. The dsPIC30F
CPU requires all word accesses to be aligned to an even address boundary.
2. A bit manipulation instruction using the Indirect Addressing mode with the LSb of the
effective address set to ‘1’.
3. A data fetch from unimplemented data address space is attempted.
4. Execution of a “BRA #literal” instruction or a “GOTO #literal” instruction, where
literal is an unimplemented program memory address.
5. Executing instructions after modifying the PC to point to unimplemented program memory
addresses. The PC may be modified by loading a value into the stack and executing a
RETURN instruction.
Data space writes will be inhibited whenever an address error trap occurs, so that data is not
destroyed.
An address error can be detected in software by polling the ADDRERR status bit (INTCON1<3>).
To avoid re-entering the Trap Service Routine, the ADDRERR status flag must be cleared in
software prior to returning from the trap with a RETFIE instruction.
6.2.3 Disable Interrupts Instruction
The DISI (disable interrupts) instruction has the ability to disable interrupts for up to 16384
instruction cycles. This instruction is useful when time critical code segments must be executed.
The DISI instruction only disables interrupts with priority levels 1-6. Priority level 7 interrupts and
all trap events still have the ability to interrupt the CPU when the DISI instruction is active.
The DISI instruction works in conjunction with the DISICNT register. When the DISICNT register
is non-zero, priority level 1-6 interrupts are disabled. The DISICNT register is decremented on
each subsequent instruction cycle. When the DISICNT register counts down to ‘0’, priority
level 1-6 interrupts will be re-enabled. The value specified in the DISI instruction includes all
cycles due to PSV accesses, instruction stalls, etc.
The DISICNT register is readable and writable. The user can terminate the effect of a previous
DISI instruction early by clearing the DISICNT register. The amount of time that interrupts are
disabled can also be increased by writing to or adding to DISICNT.
Note: In the MAC class of instructions, the data space is split into X and Y spaces. In these
instructions, unimplemented X space includes all of Y space, and unimplemented Y
space includes all of X space.
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