Microchip Technology dsPIC30F - Page 23

© 2004 Microchip Technology Inc. DS70049C-page 2-5
Section 2. CPU
CPU
2
Figure 2-2: Programmer’s Model
NOVSZC
TBLPAG
22
0
7
0
015
Program Counter
Data Table Page Address
Status Register
Working/Address
Registers
DSP Operand
Registers
W0 (WREG)
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
Frame Pointer/W14
Stack Ptr/W15
DSP Address
Registers
39 031
DSP
Accumulators
PSVPAG
7
0
Program Space Visibility
RA
0
OA OB SA SB
RCOUNT
15
0
REPEAT Loop Counter
DCOUNT
15
0
DO Loop Counter
DOSTART
22
0
DO Loop Start Address
DOEND
DO Loop End Address
IPL<2:0>
SPLIM
Stack Pointer Limit
15
22
0
SRL
PUSH.S and POP.S Shadows
0
0
OAB SAB
Page Address
DA DC
CORCON
15
0
Core Control Register
ACCAH
ACCAL
ACCAU
ACCBU ACCBH ACCBL
ACCA
ACCB
SRH
0
0
Note: DCOUNT, DOSTART and DOEND have one level of shadow registers (not shown) for nested DO loops.