dsPIC30F Family Reference Manual
DS70059C-page 12-12 © 2004 Microchip Technology Inc.
12.4.4 Timer Operation with Fast External Clock Source
In some applications, it may be desirable to use one of the timers to count clock edges from a
relatively high frequency external clock source. In these situations, Type A and Type B time
bases are the most suitable choices for counting the external clock source, because the clock
synchronization logic for these timers is located after the timer prescaler (see Figure 12-1 and
Figure 12-2). This allows a higher external clock frequency to be used that will not violate the
minimum high and low times required by the prescaler. When a timer prescaler ratio other than
1:1 is selected for a Type A or Type B time base, the minimum high and low times for the external
clock input are reduced by the chosen prescaler ratio.
A Type A time base is unique because it can be operated in an Asynchronous Clock mode,
eliminating any prescaler timing requirements.
Note that in all cases, there are minimum high and low times for the external clock signal that
cannot be exceeded. These minimum times are required to satisfy the I/O pin timing
requirements.
Please refer to the device data sheet for the external clock timing specifications associated with
the time bases.
12.4.5 Gated Time Accumulation Mode
The Gated Time Accumulation mode allows the internal timer register to increment based upon
the duration of the high time applied to the TxCK pin. In the Gated Time Accumulation mode, the
timer clock source is derived from the internal system clock. When the TxCK pin state is high, the
timer register will count up until a period match has occurred, or the TxCK pin state is changed
to a low state. A pin state transition from high to low will set the TxIF interrupt flag. Depending on
when the edge occurs, the interrupt flag is asserted 1 or 2 instruction cycles after the falling edge
of the signal on the TxCK pin.
The TGATE control bit (TxCON<6>) must be set to enable the Gated Time Accumulation mode.
The timer must be enabled, TON (TxCON<15>) = 1, and the timer clock source set to the internal
clock, TCS (TxCON<1>) = 0.
The gate operation starts on a rising edge of the signal applied to the TxCK pin and terminates
on the falling edge of the signal applied to the TxCK pin. The respective timer will increment while
the external gate signal is high.
The falling edge of the gate signal terminates the count operation, but does not reset the timer.
The user must reset the timer if it is desired to start from zero on the next rising edge gate input.
The falling edge of the gate signal generates an interrupt.
The resolution of the timer count is directly related to the timer clock period. For a timer prescaler
of 1:1, the timer clock period is one instruction cycle. For a timer prescaler of 1:256, the timer
clock period is 256 times the instruction cycle. The timer clock resolution can be associated to
the pulse width of the gate signal. Refer to the “Electrical Specifications” section in the device
data sheet for further details on the gate width pulse requirements.
Note: The timer will not interrupt the CPU when a timer period match occurs in Gate Time
Accumulation mode.
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