Microchip Technology dsPIC30F - Page 367

© 2004 Microchip Technology Inc. DS70063C-page 16-15
Section 16. Quadrature Encoder Interface (QEI)
Quadrature Encoder
Interface (QEI)
16
16.5.3.2 IMV Control Bits
The IMV<2:0> control bits are available on some dsPIC devices that have the QEI module. (See
Register 16-3). These control bits allow the user to select the state of the QEA and QEB signals
for which an index pulse reset will occur.
Devices that do not have these control bits will select the QEA and QEB states automatically
during the first occurrence of an index pulse.
16.5.3.3 Index Pulse Status
The INDEX bit (QEICON<12>) provides status of the logic state on the index pin. This status bit
is very useful in position control systems during the “homing” sequence, where the system
searches for a reference position. The index bit indicates the status of the index pin after being
processed by the digital filter, if it is enabled.
16.5.3.4 Using the Index Pin and MAXCNT for Error Checking
When the counter operates in reset on index pulse mode, the QEI will also detect POSCNT
register boundary conditions. This may be used to detect system errors in the incremental
encoder system.
For example, assume a wheel encoder has 100 lines. When utilized in x4 measurement mode
and reset on the index pulse, the counter should count from 0 to 399 (0x018E) and reset. If the
POSCNT register ever achieves the values of 0xFFFF or 0x0190, some sort of system error
has occurred.
The contents of the POSCNT register is compared with MAXCNT + 1, if counting up, and with
0xFFFF, if counting down. If the QEI detects one of these values, a position count error
condition is generated by setting the CNTERR bit (QEICON<15>) and optionally generating a
QEI interrupt.
If the CEID control bit (DFLTCON<8>) is cleared (default), then a QEI interrupt will be generated
when a position count error is detected. If the CEID control bit is set, then an interrupt will not
occur.
The position counter continues to count encoder edges after detecting a position count error. No
interrupt is generated for subsequent position count error events until CNTERR is cleared by
the user.
16.5.3.5 Position Counter Reset Enable
The position counter reset enable bit, POSRES (QEICON<2>) enables reset of the position
counter when the index pulse is detected. This bit only applies when the QEI module is
configured for modes, QEIM<2:0> = ‘100’ or ‘110’.
If the POSRES bit is set to a logic ‘1’ then the position counter is reset when the index pulse is
detected as described in this section.
If the POSRES bit is set to a logic ‘0’, then the position counter is not reset when the index pulse
is detected. The position counter will continue counting up or down and be reset on the rollover
or underflow condition. The QEI continues to generate interrupts on the detection of the index
pulse.