dsPIC30F Family Reference Manual
DS70049C-page 2-20 © 2004 Microchip Technology Inc.
2.6.1 Data Accumulators
There are two 40-bit data accumulators, ACCA and ACCB, that are the result registers for the
DSP instructions listed in Table 2-3. Each accumulator is memory mapped to three registers,
where ‘x’ denotes the particular accumulator:
• ACCxL: ACCx<15:0>
• ACCxH: ACCx<31:16>
• ACCxU: ACCx<39:32>
For fractional operations that use the accumulators, the radix point is located to the right of
bit 31. The range of fractional values that be stored in each accumulator is -256.0 to
(256.0 – 2
-31
). For integer operations that use the accumulators, the radix point is located to the
right of bit 0. The range of integer values that can be stored in each accumulator is
-549,755,813,888 to 549,755,813,887.
2.6.2 Multiplier
The dsPIC30F features a 17-bit x 17-bit multiplier which is shared by both the MCU ALU and the
DSP engine. The multiplier is capable of signed or unsigned operation and can support either
1.31 fractional (Q.31) or 32-bit integer results.
The multiplier takes in 16-bit input data and converts the data to 17-bits. Signed operands to the
multiplier are sign-extended. Unsigned input operands are zero-extended. The 17-bit conversion
logic is transparent to the user and allows the multiplier to support mixed sign and
unsigned/unsigned multiplication.
The IF control bit (CORCON<0>) determines integer/fractional operation for the instructions
listed in Table 2-3. The IF bit does not affect MCU multiply instructions listed in Table 2-4, which
are always integer operations. The multiplier scales the result one bit to the left for fractional
operation. The LSbit of the result is always cleared. The multiplier defaults to Fractional mode for
DSP operations at a device Reset.
The representation of data in hardware for each of these modes is as follows:
• Integer data is inherently represented as a signed two’s complement value, where the
MSbit is defined as a sign bit. Generally speaking, the range of an N-bit two’s
complement integer is -2
N-1
to 2
N-1
– 1.
• Fractional data is represented as a two’s complement fraction where the MSbit is
defined as a sign bit and the radix point is implied to lie just after the sign bit (Q.X
format). The range of an N-bit two’s complement fraction with this implied radix point is
-1.0 to (1 – 2
1-N
).
Figure 2-9 and Figure 2-10 illustrate how the multiplier hardware interprets data in Integer and
Fractional modes. The range of data in both Integer and Fractional modes is listed in Table 2-2.
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