© 2004 Microchip Technology Inc. DS70064C-page 17-9
Section 17. 10-bit A/D Converter
10-bit A/D
Converter
17
Register 17-4: ADCHS: A/D Input Select Register
Upper Byte:
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH123NB<1:0> CH123SB CH0NB CH0SB<3:0>
bit 15 bit 8
Lower Byte:
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH123NA<1:0> CH123SA CH0NA CH0SA<3:0>
bit 7 bit 0
bit 15-14 CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for MUX B Multiplexer Setting bits
Same definition as bits 6-7 (see Note)
bit 13 CH123SB: Channel 1, 2, 3 Positive Input Select for MUX B Multiplexer Setting bit
Same definition as bit 5 (see Note)
bit 12 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit
Same definition as bit 4 (see Note)
bit 11-8 CH0SB<3:0>: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits
Same definition as bits 3-0 (see Note)
bit 7-6 CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for MUX A Multiplexer Setting bits
11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11
10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8
0x = CH1, CH2, CH3 negative input is V
REF-
bit 5 CH123SA: Channel 1, 2, 3 Positive Input Select for MUX A Multiplexer Setting bit
1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
bit 4 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is V
REF-
bit 3-0 CH0SA<3:0>: Channel 0 Positive Input Select for MUX A Multiplexer Setting bits
1111 = Channel 0 positive input is AN15
1110 = Channel 0 positive input is AN14
1101 = Channel 0 positive input is AN13
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0001 = Channel 0 positive input is AN1
0000 = Channel 0 positive input is AN0
Note: The analog input multiplexer supports two input setting configurations, denoted MUX A and MUX
B. ADCHS<15:8> determine the settings for MUX B, and ADCHS<7:0> determine the settings
for MUX A. Both sets of control bits function identically.
Note: The ADCHS register description and functionality will vary depending on the number of A/D
inputs available on the selected device. Please refer to the specific device data sheet for
additional details on this register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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