© 2004 Microchip Technology Inc. DS70064C-page 17-15
Section 17. 10-bit A/D Converter
10-bit A/D
Converter
17
17.8.2.1 Specifying Alternating Channel 0 Input Selections
The ALTS bit (ADCON2<0>) causes the module to alternate between two sets of inputs that are
selected during successive samples.
The inputs specified by CH0SA<3:0>, CH0NA, CHXSA and CHXNA<1:0> are collectively called
the MUX A inputs. The inputs specified by CH0SB<3:0>, CH0NB, CHXSB and CHXNB<1:0> are
collectively called the MUX B inputs. When the ALTS bit is ‘1’ , the module will alternate between
the MUX A inputs on one sample and the MUX B inputs on the subsequent sample.
For channel 0, if the ALTS bit is ‘0’, only the inputs specified by CH0SA<3:0> and CH0NA are
selected for sampling.
If the ALTS bit is ’1’, on the first sample/convert sequence for channel 0, the inputs specified by
CH0SA<3:0> and CH0NA are selected for sampling. On the next sample convert sequence for
channel 0, the inputs specified by CH0SB<3:0> and CH0NB are selected for sampling. This
pattern will repeat for subsequent sample conversion sequences.
Note that if multiple channels (CHPS = 01 or 1x) and simultaneous sampling (SIMSAM = 1) are
specified, alternating inputs will change every sample because all channels are sampled on
every sample time. If multiple channels (CHPS = 01 or 1x) and sequential sampling (SIMSAM
= 0) are specified, alternating inputs will change only on each sample of a particular channel.
17.8.2.2 Scanning Through Several Inputs with Channel 0
Channel 0 has the ability to scan through a selected vector of inputs. The CSCNA bit
(ADCON2<10>) enables the CH0 channel inputs to be scanned across a selected number of
analog inputs. When CSCNA is set, the CH0SA<3:0> bits are ignored.
The ADCSSL register specifies the inputs to be scanned. Each bit in the ADCSSL register
corresponds to an analog input. Bit 0 corresponds to AN0, bit 1 corresponds to AN1 and so on.
If a particular bit in the ADCSSL register is ‘1’, the corresponding input is part of the scan
sequence. The inputs are always scanned from lower to higher numbered inputs, starting at the
first selected channel after each interrupt occurs.
The ADCSSL bits only specify the input of the positive input of the channel. The CH0NA bit still
selects the input of the negative input of the channel during scanning.
If the ALTS bit is ‘1’, the scanning only applies to the MUX A input selection. The MUX B input
selection, as specified by the CH0SB<3:0>, will still select the alternating channel 0 input. When
the input selections are programmed in this manner, the channel 0 input will alternate between a
set of scanning inputs specified by the ADCSSL register and a fixed input specified by the
CH0SB bits.
Note: If the number of scanned inputs selected is greater than the number of samples
taken per interrupt, the higher numbered inputs will not be sampled.
To Next Page
Loading...
