dsPIC30F Family Reference Manual
DS70065C-page 18-8 © 2004 Microchip Technology Inc.
Register 18-4: ADCHS: A/D Input Select Register
Upper Byte:
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — CH0NB CH0SB<3:0>
bit 15 bit 8
Lower Byte:
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — CH0NA CH0SA<3:0>
bit 7 bit 0
bit 15-13 Unimplemented: Read as ‘0’
bit 12 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit
Same definition as bit <4> (see Note 1).
bit 11-8 CH0SB<3:0>: Channel 0 Positive Input Select for MUX B Multiplexer Setting bit
Same definition as bits <3:0> (see Note 1).
bit 7-5 Unimplemented: Read as ‘0’
bit 4 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is V
REF-
bit 3-0 CH0SA<3:0>: Channel 0 Positive Input Select for MUX A Multiplexer Setting bit
1111 = Channel 0 positive input is AN15
1110 = Channel 0 positive input is AN14
1101 = Channel 0 positive input is AN13
·····
0001 = Channel 0 positive input is AN1
0000 = Channel 0 positive input is AN0
Note: The analog input multiplexer supports two input setting configurations, denoted MUX A and
MUX B. ADCHS<15:8> determines the settings for MUX B, and ADCHS<7:0> determines the
settings for MUX A. Both sets of control bits function identically.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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