© 2004 Microchip Technology Inc. DS70049C-page 2-31
Section 2. CPU
CPU
2
2.9.1.2 Interrupting a REPEAT Loop
A REPEAT instruction loop may be interrupted at any time.
The RA state is preserved on the stack during exception processing to allow the user to execute
further REPEAT loops from within (any number) of nested interrupts. After SRL is stacked, the
RA status bit is cleared to restore normal execution flow within the ISR.
Returning into a Repeat loop from an ISR using RETFIE requires no special handling. Interrupts
will pre-fetch the repeated instruction during the third cycle of the RETFIE. The stacked RA bit
will be restored when the SRL register is popped and, if set, the interrupted Repeat loop will be
resumed.
2.9.1.2.1 Early Termination of a Repeat Loop
An interrupted Repeat loop can be terminated earlier than normal in the ISR by clearing the
RCOUNT register in software.
2.9.1.3 Restrictions on the REPEAT Instruction
Any instruction can immediately follow a REPEAT except for the following:
1. Program Flow Control instructions (any branch, compare and skip, subroutine calls,
returns, etc.).
2. Another REPEAT or DO instruction.
3. DISI, ULNK, LNK, PWRSAV, RESET.
4. MOV.D instruction.
Note: If a Repeat loop has been interrupted and an ISR is being processed, the user must
stack the RCOUNT (Repeat Count register) prior to executing another REPEAT
instruction within an ISR.
Note: If Repeat was used within an ISR, the user must unstack RCOUNT prior to executing
RETFIE.
Note: Should the repeated instruction (target instruction in the Repeat loop) be accessing
data from PS using PSV, the first time it is executed after a return from an exception
will require 2 instruction cycles. Similar to the first iteration of a loop, timing limita-
tions will not allow the first instruction to access data residing in PS in a single
instruction cycle.
Note: There are some instructions and/or Instruction Addressing modes that can be
executed within a Repeat loop, but make little sense when repeated.
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