© 2004 Microchip Technology Inc. DS70067C-page 20-5
Section 20. Serial Peripheral Interface (SPI)
Serial Peripheral
Interface (SPI)
20
Register 20-2: SPIXCON: SPIx Control Register
Upper Byte:
U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— FRMEN SPIFSD — DISSDO MODE16 SMP CKE
bit 15 bit 8
Lower Byte:
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SSEN CKP MSTEN SPRE<2:0> PPRE<1:0>
bit 7 bit 0
bit 15 Unimplemented: Read as ‘0’
bit 14 FRMEN: Framed SPI Support bit
1 = Framed SPI support enabled
0 = Framed SPI support disabled
bit 13 SPIFSD: Frame Sync Pulse Direction Control on SSx
pin bit
1 = Frame sync pulse input (slave)
0 = Frame sync pulse output (master)
bit 12 Unimplemented: Read as ‘0’
bit 11 DISSDO: Disable SDOx pin bit
1 = SDOx pin is not used by module. Pin is controlled by associated port register.
0 = SDOx pin is controlled by the module
bit 10 MODE16: Word/Byte Communication Select bit
1 = Communication is word-wide (16 bits)
0 = Communication is byte-wide (8 bits)
bit 9 SMP: SPI Data Input Sample Phase bit
Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 8 CKE: SPI Clock Edge Select bit
1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6)
0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6)
Note: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the
Framed SPI modes (FRMEN = 1).
bit 7 SSEN: Slave Select Enable (Slave mode) bit
1 = SS
pin used for Slave mode
0 = SS
pin not used by module. Pin controlled by port function.
bit 6 CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 5 MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
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