© 2004 Microchip Technology Inc. DS70049C-page 2-33
Section 2. CPU
CPU
2
2.9.2.2 DO Loop Nesting
The DOSTART, DOEND and DCOUNT registers each have a shadow register associated with
them, such that the DO loop hardware supports one level of automatic nesting. The DOSTART,
DOEND and DCOUNT registers are user accessible and they may be manually saved to permit
additional nesting, where required.
The DO Level bits, DL<2:0> (CORCON<10:8>) indicate the nesting level of the DO loop currently
being executed. When the first DO instruction is executed, DL<2:0> is set to B‘001’ to indicate
that one level of DO loop is underway. The DA (SR<9>) is also set. When another DO instruction
is executed within the first DO loop, the DOSTART, DOEND and DCOUNT registers are
transferred into the shadow registers, prior to being updated with the new loop values. The
DL<2:0> bits are set to B‘010’ indicating that a second, nested DO loop is in progress. The DA
(SR<9>) bit also remains set.
If no more than one level of DO loop nesting is required in the application, no special attention is
required. Should the user require more than one level of DO loop nesting, this may be achieved
through manually saving the DOSTART, DOEND and DCOUNT registers prior to executing the
next DO instruction. These registers should be saved whenever DL<2:0> is B’010’ or greater.
The DOSTART, DOEND and DCOUNT registers will automatically be restored from their shadow
registers when a DO loop terminates and DL<2:0> = B’010’.
2.9.2.3 Interrupting a DO Loop
DO loops may be interrupted at any time. If another DO loop is to be executed during the ISR,
the user must check the DL<2:0> status bits and save the DOSTART, DOEND and DCOUNT
registers as required.
No special handling is required if the user can ensure that only one level of DO loop will ever be
executed in:
• both background and any one ISR handler (if interrupt nesting is enabled) or
• both background and any ISR (if interrupt nesting is disabled)
Alternatively, up to two (nested) DO loops may be executed in either background or within any
•one ISR handler (if interrupt nesting is enabled) or
• in any ISR (if interrupt nesting is disabled)
It is assumed that no DO loops are used within any trap handlers.
Returning to a DO loop from an ISR, using the RETFIE instruction, requires no special handling.
2.9.2.4 Early Termination of the DO loop
There are two ways to terminate a DO loop, earlier than normal:
1. The EDT (CORCON<11>) bit provides a means for the user to terminate a DO loop before
it completes all loops. Writing a ‘1’ to the EDT bit will force the loop to complete the
iteration underway and then terminate. If EDT is set during the penultimate or last
instruction of the loop, one more iteration of the loop will occur. EDT will always read as a
‘0’; clearing it has no effect. After the EDT bit is set, the user can optionally branch out of
the DO loop.
2. Alternatively, the code may branch out of the loop at any point except from the last instruc-
tion, which cannot be a flow control instruction. Although the DA bit enables the DO loop
hardware, it will have no effect unless the address of the penultimate instruction is
encountered during an instruction pre-fetch. This is not a recommended method for
terminating a DO loop.
Note: The DL<2:0> (CORCON<10:8>) bits are combined (logically OR-ed) to form the DA
(SR<9>) bit. If nested DO loops are being executed, the DA bit is cleared only when
the loop count associated with the outer most loop expires.
Note: Exiting a DO loop without using EDT is not recommended because the hardware
will continue to check for DOEND addresses.
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