© 2004 Microchip Technology Inc. DS70049C-page 2-39
Section 2. CPU
CPU
2
CORCON 0044 — — — US EDT DL2 DL<1:0> SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0000 0000 0010 0000
MODCON 0046 XMODEN YMODEN
— — BWM<3:0> YWM<3:0> XWM<3:0>
0000 0000 0000 0000
XMODSRT 0048 XMODSRT<15:0> 0
xxxx xxxx xxxx xxx0
XMODEND 004A XMODEND<15:0> 1
xxxx xxxx xxxx xxx1
YMODSRT 004C YMODSRT<15:0> 0
xxxx xxxx xxxx xxx0
YMODEND 004E YMODEND<15:0> 1
xxxx xxxx xxxx xxx1
XBREV 0050 BREN XBREV<14:0>
xxxx xxxx xxxx xxxx
DISICNT 0052
— — DISICNT<13:0>
0000 0000 0000 0000
Reserved 0054 -
007E
— — — — — — — — — — — — — — — —
0000 0000 0000 0000
Legend: x = uninitiated
Note: Refer to the device data sheet for specific Core Register Map details.
Table 2-8: dsPIC30F Core Register Map (Continued)
Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State
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