© 2004 Microchip Technology Inc. DS70070B-page 23-3
Section 23. CAN
CAN Module
23
23.2.1 CAN Control and Status Registers
Register 23-1: CiCTRL: CAN Module Control and Status Register
Upper Byte:
R/W-x U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0
TSTAMP
— CSIDL ABAT CANCKS REQOP<2:0>
bit 15 bit 8
Lower Byte:
R-1 R-0 R-0 U-0 R-0 R-0 R-0 U-0
OPMODE<2:0>
— ICODE<2:0> —
bit 7 bit 0
bit 15 TSTAMP: CAN Message Receive Capture Enable bit
1 = Enable CAN capture
0 = Disable CAN capture
Note: TSTAMP is always writable, regardless of CAN module Operating mode.
bit 14 Unimplemented: Read as ‘0’
bit 13 CSIDL: Stop in Idle Mode bit
1 = Discontinue CAN module operation when device enters Idle mode
0 = Continue CAN module operation in Idle mode
bit 12 ABAT: Abort All Pending Transmissions bit
1 = Abort pending transmissions in all Transmit Buffers
0 = No effect
Note: Module will clear this bit when all transmissions aborted.
bit 11 CANCKS: CAN Master Clock Select bit
1 = F
CAN clock is FCY
0 = FCAN clock is 4 FCY
bit 10-8 REQOP<2:0>: Request Operation Mode bits
111 = Set Listen All Messages mode
110 = Reserved
101 = Reserved
100 = Set Configuration mode
011 = Set Listen Only mode
010 = Set Loopback mode
001 = Set Disable mode
000 = Set Normal Operation mode
bit 7-5 OPMODE<2:0>: Operation Mode bits
Note: These bits indicate the current Operating mode of the CAN module. See description for REQOP
bits (CiCTRL<10:8>).
bit 4 Unimplemented: Read as ‘0’
To Next Page
Loading...
