Microchip Technology dsPIC30F - Page 603

© 2004 Microchip Technology Inc. DS70070B-page 23-5
Section 23. CAN
CAN Module
23
23.2.2 CAN Transmit Buffer Registers
This subsection describes the CAN Transmit Buffer Register and the associated Transmit Buffer
Control Registers.
Register 23-2: CiTXnCON: Transmit Buffer Status and Control Register
Upper Byte:
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
Lower Byte:
U-0 R-0 R-0 R-0 R/W-0 U-0 R/W-0 R/W-0
— TXABT TXLARB TXERR TXREQ —TXPRI<1:0>
bit 7 bit 0
bit 15-7 Unimplemented: Read as '0'
bit 6 TXABT: Message Aborted bit
1 = Message was aborted
0 = Message has not been aborted
Note: This bit is cleared when TXREQ is set.
bit 5 TXLARB: Message Lost Arbitration bit
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
Note: This bit is cleared when TXREQ is set.
bit 4 TXERR: Error Detected During Transmission bit
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
Note: This bit is cleared when TXREQ is set.
bit 3 TXREQ: Message Send Request bit
1 = Request message transmission
0 = Abort message transmission if TXREQ already set, otherwise no effect
Note: The bit will automatically clear when the message is successfully sent.
bit 2 Unimplemented: Read as ‘0’
bit 1-0 TXPRI<1:0>: Message Transmission Priority bits
11 = Highest message priority
10 = High intermediate message priority
01 = Low intermediate message Priority
00 = Lowest message priority
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown