Microchip Technology dsPIC30F - Page 606

dsPIC30F Family Reference Manual
DS70070B-page 23-8 © 2004 Microchip Technology Inc.
23.2.3 CAN Receive Buffer Registers
This subsection shows the Receive buffer registers with their associated control registers.
Register 23-7: CiRX0CON: Receive Buffer 0 Status and Control Register
Upper Byte:
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
Lower Byte:
R/C-0 U-0 U-0 U-0 R-0 R/W-0 R/W-0 R-0
RXFUL
— — — RXRTRRO DBEN JTOFF FILHIT0
bit 7 bit 0
bit 15-8 Unimplemented: Read as ‘0’
bit 7 RXFUL: Receive Full Status bit
1
= Receive buffer contains a valid received message
0 = Receive buffer is open to receive a new message
Note: This bit is set by the CAN module and should be cleared by software after the buffer is read.
bit 6-4 Unimplemented: Read as ‘0’
bit 3 RXRTRRO: Received Remote Transfer Request bit (read only)
1 = Remote Transfer Request was received
0 = Remote Transfer Request not received
Note: This bit reflects the status of the last message loaded into Receive Buffer 0.
bit 2 DBEN: Receive Buffer 0 Double Buffer Enable bit
1 = Receive Buffer 0 overflow will write to Receive Buffer 1
0 = No Receive Buffer 0 overflow to Receive Buffer 1
bit 1 JTOFF: Jump Table Offset bit (read only copy of DBEN)
1 = Allows Jump Table offset between 6 and 7
0 = Allows Jump Table offset between 0 and 1
bit 0 FILHIT0: Indicates Which Acceptance Filter Enabled the Message Reception bit
1 = Acceptance Filter 1 (RXF1)
0 = Acceptance Filter 0 (RXF0)
Note: This bit reflects the status of the last message loaded into Receive Buffer 0.
Legend:
R = Readable bit W = Writable bit C = Bit can be cleared U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown