dsPIC30F Family Reference Manual
DS70070B-page 23-50 © 2004 Microchip Technology Inc.
Figure 23-12: Transmit Buffers
23.7.3 Transmit Message Priority
Transmit priority is a prioritization within each node of the pending transmittable messages. Prior
to sending the SOF (Start-Of-Frame), the priorities of all buffers ready for transmission are
compared. The Transmit Buffer with the highest priority will be sent first. For example, if Transmit
Buffer 0 has a higher priority setting than Transmit Buffer 1, Buffer 0 will be sent first. If two buffers
have the same priority setting, the buffer with the highest address will be sent. For example, if
Transmit Buffer 1 has the same priority setting as Transmit Buffer 0, Buffer 1 will be sent first.
There are 4 levels of transmit priority. If TXPRI<1:0> (CiTXnCON<1:0>) for a particular message
buffer is set to ‘11’, that buffer has the highest priority. If TXPRI<1:0> for a particular message
buffer is set to ‘10’ or ‘01’, that buffer has an intermediate priority. If TXPRI<1:0> for a particular
message buffer is ‘00’, that buffer has the lowest priority.
23.7.4 Message Transmission
To initiate transmitting the message, the TXREQ bit (CiTXnCON<3>) must be set. The CAN bus
module resolves any timing conflicts between setting of the TXREQ bit and the SOF time,
ensuring that if the priority was changed, it is resolved correctly before SOF. When TXREQ is set
the TXABT (CiTXnCON<6>), TXLARB (CiTXnCON<5>) and TXERR (CiTXnCON<4>) flag bits
will be cleared by the module.
Setting TXREQ bit does not actually start a message transmission, it flags a message buffer as
enqueued for transmission. Transmission will start when the module detects an available bus for
SOF. The module will then begin transmission on the message which has been determined to
have the highest priority.
If the transmission completes successfully on the first try, the TXREQ bit will clear and an
interrupt will be generated if the TXnIE bit (CiINTE<2>, CiINTE<3>, CiINTE<4>) is set.
If the message fails to transmit, other condition flags will be set and the TXREQ bit will remain
set indicating that the message is still pending for transmission. If the message tried to transmit
but encountered an error condition, the TXERR bit (CiTXnCON<4>) will be set. In this case, the
error condition can also cause an interrupt. If the message tried to transmit but lost arbitration,
the TXLARB bit (CiTXnCON<5>) will be set. In this case, no interrupt is available to signal the
loss of arbitration.
TXREQ
TXB0
TXABT
TXLARB
TXERR
TXPRI
MESSAGE
Message
Queue
Control
Transmit Byte Sequencer
TXREQ
TXB1
TXABT
TXLARB
TXERR
TXPRI
MESSAGE
TXREQ
TXB2
TXABT
TXLARB
TXERR
TXPRI
MESSAGE
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