dsPIC30F Family Reference Manual
DS70070B-page 23-62 © 2004 Microchip Technology Inc.
23.9.3 Propagation Segment
This part of the bit time is used to compensate physical delay times within the network. These
delay times consist of the signal propagation time on the bus line and the internal delay time of
the nodes. The delay is calculated as the round trip from transmitter to receiver as twice the
signal's propagation time on the bus line, the input comparator delay, and the output driver delay.
The Propagation Segment can be programmed from 1 T
Q to 8 TQ by setting the PRSEG<2:0>
bits (CiCFG2<2:0>).
23.9.4 Phase Segments
The phase segments are used to optimally locate the sampling of the received bit within the
transmitted bit time. The sampling point is between Phase1 Segment and Phase2 Segment.
These segments are lengthened or shortened by re-synchronization. The end of the Phase1
Segment determines the sampling point within a bit period. The segment is programmable from
1T
Q to 8 TQ. Phase2 Segment provides delay to the next transmitted data transition. The
segment is programmable from 1 T
Q to 8 TQ or it may be defined to be equal to the greater of
Phase1 Segment or the Information Processing Time (3 T
Q’s). The phase segment 1 is initialized
by setting bits SEG1PH<2:0> (CiCFG2<5:3>), and phase segment 2 is initialized by setting
SEG2PH<2:0> (CiCFG2<10:8>).
23.9.5 Sample Point
The sample point is the point of time at which the bus level is read and interpreted as the value
of that respective bit. The location is at the end of phase segment 1. If the bit timing is slow and
contains many T
Q, it is possible to specify multiple sampling of the bus line at the sample point.
The level determined by the CAN bus then corresponds to the result from the majority decision
of three values. The majority samples are taken at the sample point and twice before with a
distance of T
Q/2. The CAN module allows to chose between sampling three times at the same
point or once at the same point. This is done by setting or clearing the SAM bit (CiCFG2<6>).
23.9.6 Synchronization
To compensate for phase shifts between the oscillator frequencies of the different bus stations,
each CAN controller must be able to synchronize to the relevant signal edge of the incoming
signal. When an edge in the transmitted data is detected, the logic will compare the location of
the edge to the expected time (Synchronous Segment). The circuit will then adjust the values of
Phase1 Segment and Phase2 Segment. There are 2 mechanisms used to synchronize.
23.9.6.1 Hard Synchronization
Hard Synchronization is only done whenever there is a “recessive” to “dominant” edge during bus
Idle, indicating the start of a message. After hard synchronization, the bit time counters are
restarted with Synchronous Segment. Hard synchronization forces the edge which has caused
the hard synchronization to lie within the synchronization segment of the restarted bit time.
Due to the rules of synchronization, if a hard synchronization is done, there will not be a
re-synchronization within that bit time.
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