Microchip Technology dsPIC30F - Page 665

© 2004 Microchip Technology Inc. DS70070B-page 23-67
Section 23. CAN
CAN Module
23
Figure 23-23: Processor Sleep and CAN bus Wake-up Interrupt
23.13.2 CAN Module Operation during CPU Idle Mode
On executing a CPU Idle (PWRSAV #1) instruction, the operation of the CAN module is
determined by the state of the CSIDL bit (CiCTRL<13>).
If CSIDL = 0, the module will continue operation on assertion of Idle mode. The CAN module can
wake the device from Idle mode if the CAN module interrupt is enabled.
If CSIDL = 1, the module will discontinue operation in Idle mode. The same rules and conditions
for entry to and wake from Sleep mode apply. Refer to Section 23.13.1 “Operation in Sleep
Mode” for further details.
TOST
Processor in
S
LEEP
2 3
4 5
- Processor executes SLEEP (PWRSAV #0) instruction.
- SOF of message wakes up processor. Oscillator start time begins. CAN message lost. WAKIF bit set.
- Processor completes oscillator start time. Processor resumes program or interrupt, based on GIE bits.
accepting CAN bus activity. CAN message lost.
- Module detects 11 recessive bits. Module will begin to receive messages and transmit any pending messages.
OSC1
CAN bus
CAN Module
Disabled
001
001
000
000 000
000
Sleep
WAKIF
WAKIE
1
- Processor requests and receives Module Disable mode. Wake-up interrupt enabled.
Processor requests Normal Operating mode. Module waits for 11 recessive bits before
1
2
3
4
5
REQOP<2:0>
OPMODE<2:0>