dsPIC30F Family Reference Manual
DS70071C-page 24-4 © 2004 Microchip Technology Inc.
Register 24-2: FWDT: Watchdog Timer Configuration Register
Upper Byte:
UU UUUUUU
— — — — — — — —
bit 23 bit 16
Middle Byte:
R/P U U U U U U U
FWDTEN
— — — — — — —
bit 15 bit 8
Lower Byte:
U U R/P R/P R/P R/P R/P R/P
FWPSA<1:0> FWPSB<3:0>
bit 7 bit 0
bit 23-16 Unimplemented: Read as ‘0’
bit 15 FWDTEN: Watchdog Enable Configuration bit
1 = Watchdog Enabled (LPRC oscillator cannot be disabled. Clearing the SWDTEN bit in the RCON
register. Will have no effect.)
0 = Watchdog Disabled (LPRC oscillator can be disabled by clearing the SWDTEN bit in the RCON
register.)
bit 14-6 Unimplemented: Read as ‘0’
bit 5-4: FWPSA<1:0>: Prescale Value Selection for Watchdog Timer Prescaler A bits
11 = 1:512
10 = 1:64
01 = 1:8
00 = 1:1
bit 3-0 FWPSB<3:0>: Prescale Value Selection for Watchdog Timer Prescaler B bits
1111 = 1:16
1110 = 1:15
•
•
•
0001 = 1:2
0000 = 1:1
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit
To Next Page
Loading...
